Forum Post: Using "winding" in analogLib as a transformer
Dear All, I want to use a transformer with turn ratio and different dot positions the primary and secondary. xfmr in analoglib doesn't allow this. I am thinking to use " winding " in analogLib. First...
View ArticleForum Post: How to define keepout area (blockage) in Cadence Virtuoso Router...
Hi, I am routing with VSR in Cadence GXL layout. In Virtuoso Chip assembly Router there is an option to define the keepout area. I don't know how to define a blockage in VSR. Would you please help me...
View ArticleForum Post: RE: sevEvaluateAndPlotExpressions
Hey there Andrew, By plotting mode I mean underneath the outputs there are options for "Plot after simulation" and "Plotting mode", with the options of "New Subwin," "Append," "Replace," and "New Win."...
View ArticleForum Post: Can I test to see if a procedure is defined?
I am writing a skill program that at one point uses a skill procedure defined by a different skill program. Because of this, I want a way to test to see if the procedure I want to use has been defined....
View ArticleForum Post: RE: Can I test to see if a procedure is defined?
You can use getd('funcName) to determine if a function is defined. However, it's better to use isCallable('funcName) because that will tell you if either the function is defined, or would be when you...
View ArticleForum Post: How to get " the rotation & coordinate to the top " of the...
Dear All, I want to get " the rotation & coordinate to the top " of the cellname in a large layout design , but how to do it ? The cellname maybe has more than one and the layout design is very...
View ArticleForum Post: how do I attach technology library with new virtuoso lib
Hi, I copied library from design with different technology, library and each cell has data.dm, I am assuming data.dm file still has technology information of source library. How do I update library and...
View ArticleForum Post: RE: RTL compiler technology transformation
Hi gh.. Yeah I found the same while reading RTL compiler documents. And what if my new library doesn't have the integrated clock gating cell. How can I map this? And another one thing is.. The clock...
View ArticleForum Post: RE: Problem building a slotted metal pcell
When you don't have a clue what you're doing, starting with code from a 9-year old post (from the old forums) which wasn't fully functional seems an odd thing to want to do. The post references some...
View ArticleForum Post: Auto create report vs statistics for checking unrouted nets
Hello, I am using orcad layout. To check the unrouted nets, if i use Auto-> create reports and select 'Conn unrouted', it shows no unconnected nets. However, if i check the 'statistics' spreadsheet,...
View ArticleForum Post: Compare instance CDF parameters with their default values
Hi, I want to compare cdf param values of a Pcell instance in my library to that of the cdf param of same pcell in technology library. So I want to compare cdf param of my instance with their default...
View ArticleForum Post: RE: Compare instance CDF parameters with their default values
Hi Sanket, Unless all of the PCell parameters are stored on the instance (i.e. where the parameters have storeAsDefault 'true'), default values for parameters are not stored on instances. So only when...
View ArticleForum Post: RE: No DRC error when placing or sliding vias over inner traces
I have updated to 16.6 SO74 and my issue still remains. I have noticed that my design randomly changed the via padstack to "via1" but even when I changed it to "via' in the constraint manager and...
View ArticleForum Post: encryption question
Hi All, 1. I type the following command in CIW encrypt( "abc.il" , "abc_enc.il") Could anther user convert abc_enc.il to ASCII file ? 2. I type the following command in CIW encrypt( "abc.il" ,...
View ArticleForum Post: RE: encryption question
Hi ManChak, 1) potentially, simply loading the abc_enc.il file will decrypt it in virtual memory, with a SKILL debug key it could be pretty printed and/or written out. By default the function is...
View ArticleForum Post: RE: encryption question
Hi Lawrence, 1. Thank you for your info. Could you point me to the document to generate context file ? Foundry pdk uses context file, but I do not know how to generate it. 2. Regarding item 2, does the...
View ArticleForum Post: RE: sevEvaluateAndPlotExpressions
Thanks for that information. I'm still learning a lot about cadence/skill. While there is not a way to change the settings in an existing session, Would running newWindow() or newSubwindow before...
View ArticleForum Post: RE: How to get " the rotation & coordinate to the top " of the...
Andrew, Yes, It's what i want. If you can help to do deal with mosaic (w/i CDBA/OA) , it will be better . Thank you, Charley
View ArticleForum Post: RE: encryption question
Hi ManChak, 1. Look for "setContext" and "saveContext" in the documentation. I'm not going to search for you, you can type "context" in the Search box in a design window, or even in the cdnshelp tool,...
View ArticleForum Post: RE: No DRC error when placing or sliding vias over inner traces
Any way you can zip and post your board or PM it? It sounds like something is not turned on correctly or a padstack is broken.
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