Forum Post: RE: Queue list in job policies of ADE
Very hard to be certain given that you didn't give any information about what version you're using. You may need to kill off any running cdsfrb_lsf process (note that you should wait until no jobs are...
View ArticleForum Post: RE: Need help in writing Skill for routing between two different MOS
Raghu, Well, if you have the instID and termName of the terminal you're trying to locate, then you'd do something like this: term=dbFindTermByName(instID~>master termName) foreach(pin term~>pins...
View ArticleForum Post: RE: The creation of customVia failed
Adam, There isn't any SKILL support (as far as I know) for creating instances of such cdsGenVias. I found a few CCRs saying this and this is still a project to be completed. No plans to complete it...
View ArticleForum Post: RE: saving results with same net names of two different cells
Zubair, You probably (if you're using ADE L, you didn't say) have to do Results->Save after the first run to save the results under a different name, and then run the second simulation. You can then...
View ArticleForum Post: RE: variable $freq in veriloga
My latest version is MMSIM 15.10.803 As you say it might be a bit fussy as your example does work, but my current experiment is not working although it might have worked briefly before I made some...
View ArticleForum Post: RE: variable $freq in veriloga
Hi Robin, The fact that it is not documented tells me that it's not really fully released yet - because it only works in narrow cases. Even then, it's not going to work in time-domain analysis. I...
View ArticleForum Post: RE: variable $freq in veriloga
Hi Andrew, This should give an idea of what I was trying to do - a low pass with variable roll off rate. In my simulations it had a flat frequency response of 1. Regards, Robin `include "discipline.h"...
View ArticleForum Post: RE: variable $freq in veriloga
p.s. If I make the output a current and connect output to a resistor load then I get something that looks like the expected behaviour.
View ArticleForum Post: RE: How to short a net and a shape on layout using VIA
Hello Francesco Might I suggest that you do not use Net Short to fool the PCB nets. Doing this will mean that your netlist from the schematic does not actually reflect what is on the board. If you have...
View ArticleForum Post: Generating Gerber RS274X In 2:3 Format & Gerber File Syntax Issue.
Hi, I have a couple of issues with exporting gerber data from Orcad/Allegro PCB Editor (16.6) & (17.2) My first issue pertains to exporting the gerber files in a standard 2:3 Format. I work in mils...
View ArticleForum Post: RE: how to create the filled shape for selected Finger?
Hi, you could try this code: axlDBCreateShape( car( axlPolyFromDB( Finger )), t, "Substrate Geometry/outline")
View ArticleForum Post: RE: The creation of customVia failed
Hello Andrew, that's bad news, but thank you very much for clarification! I'll try to find out why this rare method is used. Best regards, Adam
View ArticleForum Post: [IC6.1.7] Simulating VHDL-AMS
I am trying to perform a simple simulation with a VHDL-AMS modeled resistor. Unfortunately I cannot simulate it. I made the following: Created a new Cell View in the Library Manager with the type...
View ArticleForum Post: RE: variable $freq in veriloga
For this purpose, you could also try to use the fracpole component. For more information, type "spectre -h fracpole" at the command line. The article at...
View ArticleForum Post: RE: [IC6.1.7] Simulating VHDL-AMS
First of all, you didn't mention which simulator you're using - but from what you've said, it can't be "ams" (which is what you need if using a Cadence simulator and want to simulate VHDL-AMS models)....
View ArticleForum Post: RE: encounter SEGV internal error (with optDesign -postRoute)
If you are getting a stack trace, and don't have any obvious errors earlier in the run that you can fix (check your complete log file first), then you need to file a service request so R&D can take...
View ArticleForum Post: RE: [Voltus] set_pg_library_mode command option -power_pins?
See the Power Grid Library Generation chapter in the Voltus User Guide. Commands should work in Innovus.
View ArticleForum Post: RE: SOC encounter: short drc error on a particular cell
Turn on cell blockages in Innovus to see why it thinks there is a short. The blockages in the cell LEF may be more general than the actual cell layout.
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