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Forum Post: Using strings in constraints to randomize data

Hi, I am using a constraint that uses a string var to randomize a random variable(data). But xcelium give me an error: Constraint: constraint data { sel_string inside {"A"} -> data[0] == 1;} Error:...

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Forum Post: RE: VPWLF source in Cadence Virtuoso

Hi Jagdish, Follow the next steps: 1. Do steps 1-8 mentioned in the below article: How can I have a vpwlf source with the filename specified with a design variable? 2. Replace the analogLib/vpwlf with...

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Forum Post: RE: Using strings in constraints to randomize data

One way to work around this is to convert the string variable to a SystemVerilog enumeration. The following code snippet illustrates this. typedef enum {A, B} sel_string_e; class foo; rand sel_string_e...

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Forum Post: RE: Using strings in constraints to randomize data

Hi, Thanks for this solution. The compilation error is gone. Thanks, Preethi

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Forum Post: RE: VPWLF source in Cadence Virtuoso

Hi Dimitra, The link you have send is asking for extra credential, such as HOST_IS & REFERENCE_KEY. How can I access that information? I tried the way you have explained in point 2 to 4. But I dont...

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Forum Post: RE: VPWLF source in Cadence Virtuoso

Hi Jagdish, This is because you skipped step 1 You need to have an account to be able to access the link on Cadence support site. It's ok I can write the steps mentioned in the link here: For step1:...

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Forum Post: RE: VPWLF source in Cadence Virtuoso

Hi Dimitra, Such a naive mistake to overlook 1st step in itself Nevertheless, I followed the procedure and now I can see the variable in ADE state. Thanks a lot. Regards, Jagdish

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Forum Post: RE: Is there a way to describe the charge across the device as a...

I would like to thank you belatedly. My model now works for the most part. I'm still working on improvements.

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Forum Post: RE: Is there a method for simulating a circuit with varying...

I got it to work, thank you.

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Forum Post: RE: terminals "cannot be found in the switched master of the...

I got it to work, thank you.

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Forum Post: RE: Can I shrink an imported schematic?

One idea to explore. When importing exported graphical information in any tool, you have to make sure that "unit of measure" are set the same for both the exporting and import tools. Otherwise, you...

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Forum Post: When does le1ViaForm get created?

I have some bindkey code that cycles through the a specified list of via types (potentially all the via types in the technology) while the Add Via enterfunction is active. The code sets...

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Forum Post: RE: When does le1ViaForm get created?

PS this is Virtuoso XL in IC6.1.7-64b.500.18

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Forum Post: RE: When does le1ViaForm get created?

oops, sorry this is Virtuoso L, not XL.

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Forum Post: adding vias to a part (symbol)

Hi I'm new to OrCAD and have only done one design so far but I'm trying to figure out how to stick vias into a thermal pad. I have a QFN design from a friend and I can't tell if he did it as well but...

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Forum Post: RE: When does le1ViaForm get created?

The form is technology file specific, so you can get more than one via form depending on if you have more than one tech lib (so it could happen if you have incremental technology databases too)....

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Forum Post: RE: When does le1ViaForm get created?

Interesting. Thanks for the quick and complete info.

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Forum Post: RE: adding vias to a part (symbol)

You can add the vias at the package level by using "add connect" in the menu. You will need a padstack for the large thermal pad and then you can add as vias as you desire to it. Be sure to add the...

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Forum Post: How to give net name while creating path from skill?

Hi, i am using dbCreatePath() function to create a path, but i dont know how to attach the net name with that path. Any suggestions? Any other function through which we can give the net name to the...

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Forum Post: RE: How to give net name while creating path from skill?

Use dbMakeNet to create the net, and dbAddFigToNet to add the newly created path to the net. Regards, Andrew

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