Forum Post: How to read current flow into a schematic symbol terminal using...
Hello SKILL experts, I am fairly new to SKILL and have a basic doubt. I have searched for a solution in the Community Technical Forums for hours but was unable to get any help. The problem is as...
View ArticleForum Post: RE: Cadence Liberate Characterization Help
Hi Anuradha, Thank you for your reply and I am sorry for my late response. I have tried with the sample run script, model file, and template provided with the Liberate tool and got the library creation...
View ArticleForum Post: compare pins from 2 symbol
How to compare pins from 2 different symbols in virtuoso using skill code ?
View ArticleForum Post: RE: Unable to edit a cellview in a RAK
Ok I just checked the env variable is set to /tmpdir What should the $TMPDIR env variable be set to? Or should I not use the variable at all? edit: The $TMPDIR env variable was set to /tmp and that...
View ArticleForum Post: Footprint Preview
Hi everyone, I'm a newbie. It's the first time I use PCB Allegro. I can't see the preview of any components, even Resistor or Capacitor. And I don't know how to add library. Please supporting me. Thank...
View ArticleForum Post: axlUnsetVariableFile not update user env for allegro_html and...
Hi all, I tried to use axlUnsetVariableFile to turn off allegro_html_qt, but it does not update the user env file. I also tried the same for allegro_html and get the same results. Other variable seem...
View ArticleForum Post: RE: axlUnsetVariableFile not update user env for allegro_html and...
I just noticed, allegro_html works, but allegro_html_qt does not.
View ArticleForum Post: RE: Need Thumbnail warnings explanation
Hi Andrew, Thank you for your idea, I haven't thought about this possibility. DesignSync is available in my system but should be disabled for this project. Maybe there are some leftover setups that...
View ArticleForum Post: access signals through hierarchy in schematic
hello experts, this is just for testing bench purpose, how can I use signals across hirarchy w/o I/O ports, e.g., I want to see BlockA/BlockSub/signalB somewhere else? thanks, David
View ArticleForum Post: IC617 output table
Hi Team, I am using IC 617 for transient simulation. After the simulation, I can plot the output waveform. However, my desired form of output would be in a table format.Moreover, for instance, I want...
View ArticleForum Post: RE: IC617 output table
Hi Allen, Do Right Mouse->Send to Calculator, and then use the sample function in the calculator to sample the signal between a start and stop time and give the step size you want. Then in the...
View ArticleForum Post: RE: access signals through hierarchy in schematic
Hi David, I'm assuming you mean that you want to connect something to those internal signals? Otherwise if it's just observing them then you can do that anyway just by selecting those signals to plot....
View ArticleForum Post: Want to add Noise in VPWL source along with ECG signal
Hello I have extracted an ECG signal I have made a .txt file with one column of amplitude and other column of time. I want to now add noise of 500 Hz in Vpwlf source. I am able to place this .txt file...
View ArticleForum Post: RE: Cadence Liberate Characterization Help
Hi Hossain, Did your characterisation run finish successfully? please check the logfile for any warning or errors. do you see INVX1 in the 'List of failing cells' at the end of your logfile? For...
View ArticleForum Post: RE: How to change background color of schematic editor in cadence...
This does not work with the version 6.17 we have, however we do have the button shown in the screen grab above, but all it does is the background colour and actually there are a whole slew of things...
View ArticleForum Post: RE: access signals through hierarchy in schematic
Hello Andrew, Exactly and working. thanks a lot, David
View ArticleForum Post: OrCad Captur CIS - How to replace to a new Title block with while...
Hi, I have a new Title Block that I want to update in my already existing designs. Is there a way to replace the Title blocks while keeping the data in the fields from the original Title Blocks on each...
View ArticleForum Post: RE: How to get via Constraint
Hi Andrew, I have some related question about viaGenerateVias* functions. It seems that it can only handle top level. How do I use them to fill via in the lower level of a cell. Thanks, Yanhong
View ArticleForum Post: Printing to a file using fprintf
Hi, I have a simulation for generating MOS transistor data using a 4 nested sweeps (VGS, L, VDS, VSB) for a 4-terminal NMOS device. I am able to setup the simulation and run it with all working OK....
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