Forum Post: Get coloring Engine status
Is there a variable to get the status or mode the coloring Engine is in when the mptDoToolbarAction("ColorEngineSwitch") is toggled? Paul
View ArticleForum Post: How to load in a Model Group file (.sdb) either in SKILL or with...
I am starting to use Explorer and would like to perform the following. Load in a previously created Model Groups file so that it is available in the simulation corners. I have a .sdb file that I...
View ArticleForum Post: RE: Get coloring Engine status
Hi Paul, I think this gives what you want: envGetVal("mpt" "coloringEngineEnabled") Best regards, Lawrence.
View ArticleForum Post: RE: running aging simulation with different bias voltage and temp...
Nasser, It can be done both from the UI and from the netlist (in Spectre native mode, for example). Regards, Andrew
View ArticleForum Post: RE: Hold time violations in post layout simulation
Further adding to the observations: The (Warning !) violations appear with worst and best corner .sdf files as well. However out_norm[1] (The data input to the Out[1] register) signal transition seems...
View ArticleForum Post: How to get the cellviews hierachy
In Virtuoso, if I have the target cell name "target", top cell name "top", lib name "mylib", view name "layout". How can I get the hierachy path for the "target" from "top"? Like hierachy path:...
View ArticleForum Post: RE: Computer specifications for Cadence Virtuoso
Thank you for your answer. I am going to talk to computer people here in school to shoot for an update and I am also going to talk to customer support. Before that, can you please let me know what do...
View ArticleForum Post: get the bBox of lower level cells in layout
Dear all, I am quite new to SKILL and I am trying to deal with db objects. What I'd like to do is to get some coordinates of sub-instances in layout, to be able then to draw certain shapes in top level...
View ArticleForum Post: Signal names in traces or pins
Hi, Is there anyway to change fond/size/hi-lite the netname in traces or pins in allegro? Thanks, TiBo
View ArticleForum Post: RE: How to get the cellviews hierachy
Hi, I think either geGetInstHierPath() or geGetInstHier() might give you what you want? Best regards, Lawrence.
View ArticleForum Post: RE: How to get the cellviews hierachy
geGetInstHierPath() and geGetInstHier() need to open a cell view and descend into or EIP in a cellview. It will not report the hier path if another cell contain the target cell. Also thanks for your...
View ArticleForum Post: RE: How to get the cellviews hierachy
Hi wenckey, Code below will get all the instance hierarchy path from top level. Hope it helps. ;procedure(CCFgetInstanceNamesAndCoords(master @optional (transform list(0:0 "R0" 1)) (hierInstPath "/"))...
View ArticleForum Post: RE: Design migration tool
Hi Andrew, You are brilliant! Please help me for the last issue: Most transistor's length is "180n" as the string, but I encountered one transistor is "400n" which showed as the number "4e-07" in SKILL...
View ArticleForum Post: black-boxing using "-bbox" in Jasper
Hi, In Japser there is a provision for black-boxing., What is the difference between: a. black-boxing during compile/analyze b. black-boxing during elaboration. -Thanks
View ArticleForum Post: RE: Design migration tool
Inside the fixing function (where you have the printf) you can put: if(numberp(val) then valAsNum=val else valAsNum=cdfParseFloatString... ) I’m writing this on a mobile device so the...
View ArticleForum Post: RE: verilog-a model help
Hi Dimitra, I was able to get some trigger info but I am still stuck with some errors. I am pasting the code below. // detect when sig rises `include "disciplines.vams" `include "constants.vams" //...
View ArticleForum Post: ODB++ Missing Pads
Hi, we are using 17.2. When we use the latest ODB++ V8 to extract files, a couple of our suppliers are saying that there are missing pads on internal layers. When we check using the ODB++ tool, we're...
View ArticleForum Post: RE: get the bBox of lower level cells in layout
Instances have a transform attribute that indicates the location and orientation of the instance relative to the cell in which it is placed. Select your I0 instance and type this in your CIW: trans =...
View ArticleForum Post: RE: Design migration tool
You are so helpful, Andrew! Now everything works perfectly！Thank you so much!
View ArticleForum Post: Voltus-Fi Peak static current analysis treatment of decoupling...
Hi, I have a couple of questions regarding how Voltus-FI static IR-drop analysis: 1. How does it treat decoupling caps and dummy or inactive transistors (Pmos with VDD-connected gates, Nmos with...
View Article