Forum Post: RE: Conflict between bus notation in Verilog ('[ ]') and Cadence...
I'm sorry, I don't know anything about Assura. I assumed you were using PVS. But there should be something equivalent. Either consult the docs, search on support.cadence.com, contact your AE, or open a...
View ArticleForum Post: Deleting stacked micro-via
Hi All, I have a 2-6-2 HDI board. the micro-vias are stacked (L1-L2, L2-L3 and L8-L9, L9-L10). The buried via is an staggered. I would like to delete L1-L2 and L9-L10 micro-via (only) using a list of...
View ArticleForum Post: Import Schematic change on PCB
Hello, I'm working on a PCB that must be updated from the schematic, I didn't make the first version of this board and I had to create a Symbol library from the existing board, some of the components...
View ArticleForum Post: This is a test (Please ignore)
Format test: procedure ( test() let ( () printf("This is a test\n") ) ;let ) ;procedure
View ArticleForum Post: RE: This is a test (Please ignore)
procedure ( test() let ( () printf("This is a test\n") ) ;let ) ;procedure
View ArticleForum Post: RE: This is a test (Please ignore)
procedure ( test() let ( () printf("This is a test\n") ) ;let ) ;procedure Testing
View ArticleForum Post: RE: This is a test (Please ignore)
procedure ( test3() let ( () printf("This is a test\n") ) ;let ) ;procedure
View ArticleForum Post: Any way to clear Line width selection drop down tab
Hi, I have a design in which i have to use different line widths. During routing, in the option tab's line width drop down there are so many unnecessary line widths are showing. I want to clear all...
View ArticleForum Post: Is there Any Way to toggle between two line widths
Hi, I have a design in which some nets should be rout with variable width. Like a net in some regions have 0.1mm width, same nets in some other regions have 0.2mm width. I want to know that is there...
View ArticleForum Post: RE: Import Schematic change on PCB
There are several things you can do that come to mind. 1) Symbols are different. Try taking the original board and doing a symbol update and saving the new board. Then import the netlist into the...
View ArticleForum Post: RE: Any way to clear Line width selection drop down tab
Yes - Invoke the Route - Connect command, select the width you want and use the backspace key until it appears blank then press Enter and you will get a popup saying do you want to delete this value....
View ArticleForum Post: Significant digits in tables generated by ADE L calculator
Hello, I would like to set 16 as the number of significant digits in the tables created through calculator from a waveform. Any suggestion? Thank you Best Regards Aldo
View ArticleForum Post: RE: Is there Any Way to toggle between two line widths
I responded to this on the other post - my mistake
View ArticleForum Post: ALT+key shortcuts are not available in 17.2 also on the latest...
On the Hotfix_SPB17.20.005_README_CCR.txt file, you can read the following text: "1588769 ALLEGRO_EDITOR UI_GENERAL ALT+key shortcuts are not available in 17.2". BUT this problem are NOT FIXED ! NOT...
View ArticleForum Post: RE: How to use PSS+PSTB or PSS+PAC to simulation the loop gain of...
Hello Andrew, Yan, I have exactly the same problem. PHI1= Auto-Zero with unit gain configuration PHI2= Amplification phase (different feedback factor) My understanding problem is following: PSTB...
View ArticleForum Post: RE: How to use PSS+PSTB or PSS+PAC to simulation the loop gain of...
Hello Andrew, Yan, I have exactly the same problem. PHI1= Auto-Zero with unit gain configuration PHI2= Amplification phase (different feedback factor) My understanding problem is following: PSTB...
View ArticleForum Post: RE: Deleting stacked micro-via
axlClearSelSet() axlSetFindFilter(?enabled list("noall", "vias", "invisible"), ?onButtons list("noall", "vias")) axlAddSelectAll() axlDeleteObject(setof(via, axlGetSelSet(), axlGeoPointsEqual(loc)...
View ArticleForum Post: spectre pss analysis failing to converge
Hi all, I have a two stage amplifier chain, and I am trying to run pac analysis on it. However, the pss analysis is failing to converge. Here is some messages from spectre. What could be done to make...
View ArticleForum Post: Edit Object Properties for the Current Source
I am doing simulations in which I intend to generate s parameters from the hybrid pi model equivalent circuit of transistor. I have a challenge on implementing the current source in cadence. The...
View ArticleForum Post: RE: Cross function
Hey, I just sorted the issue. If I use a 3rd decimal, then the cross function is not crossing, but jumping. So, I have to start the DC sweep from 0.00a, where a is the 3rd decimal.
View Article