Forum Post: RE: Why gm is not zero even when iDS is a constant DC current?
No, I will not have the time to sit and wade through Berkeley's BSIM code to answer this. Unfortunately I have enough real-world design/tool problems to worry about and can't allocate time to look at...
View ArticleForum Post: RE: Why gm is not zero even when iDS is a constant DC current?
Thank you. I appreciate your help. I am not particularly interested in this but as you may see in my other thread transconductance gm obtained from DC operating point and derivative are quite different.
View ArticleForum Post: RE: Why transconductance gm exported from DC operating point is...
Your test bench is varying Vds at the same time as Vgs, so the current is dependent upon Vds changing as well as Vgs. So taking the derivative (particularly at higher Vds) is not going to only give gm....
View ArticleForum Post: Vias in BGA routing
Hi, I'm using a controller having LFBGA package having pitch 0.5mm as shown in the attached image. I've designed the footprint for the controller. Land dia is 0.24mm. My board is having six layers and...
View ArticleForum Post: Design Entry HDL SKILL, PACK_TYPE, VALUE, cnSkill commands
Hi folks, Thanks to the PCB SKILL forum, i managed to create a few routines in skill in order to place component and wires. However i am still stuck with a lack of knowledge in the "pcb wolrd" (i am...
View ArticleForum Post: test ordering in ocean-xl
In ADE-XL when I use calcVal in one test to refer to results from another test the simulation ordering seems to be right without me doing anything special. Either that or I have just been luck. I have...
View ArticleForum Post: How to use ?modifyCallback on hiCreateStringField() properly?
Hello, For a string field of a form, I want to specify a callback function which gets triggered after each keystroke. I use the function hiCreateStringField() and I specify the ?modifyCallback to...
View ArticleForum Post: Innovus places standard cells in every 2nd row
Hi there, I am using Innovus 15.20 with a 28nm designkit and I have issues while placing the design. For whatever reason "placeDesign" omits every 2nd row: Someone out there has a clue about this?
View ArticleForum Post: RE: How to use ?modifyCallback on hiCreateStringField() properly?
Hi Sjoerd, I didn't try to get your code working in an example, but I can see what's wrong. The ?modifyCallback is expecting just the name of the function, not the function call itself. It will then...
View ArticleForum Post: RE: How to use ?modifyCallback on hiCreateStringField() properly?
Hi Andrew, Fantastic, it works! Thanks for your quick reply. With kind regards, Sjoerd
View ArticleForum Post: cdf parameter is changed when using generate all from source
Hi all, I have a schematic which consist of just one pcell. When I try to open layout of that pcell by using generate all from source feature in GXL , it should maintain the cdf parameters as in...
View ArticleForum Post: RE: cdf parameter is changed when using generate all from source
Sanket, What does: envGetVal("layoutXL" "lxEvalCDFCallbacks") and envGetVal("layoutXL" "lxCDFCallbackParams") return when you type it in the CIW? Which technology are you using? Regards, Andrew
View ArticleForum Post: RE: Renumber pin in PCB Editor
Edit->Text was no help to me. Can you please elaborate? Do I have to "enable" something? I had the pin highlighted and did this, but here is what I see in the command window below: Selected item not...
View ArticleForum Post: Reformatting of a list
Hi everybody, I have a list that look something like that: list1 = list(list("a" "1" "1") list("a" "1" "2") list("a" "2" "3") list("b" "5" "5") list("b" "5" "6") list("b" "7" "8")) and I want this list...
View ArticleForum Post: RE: Renumber pin in PCB Editor
Hello, I just got some tech support on this issue. What prevented me from altering the pin numbers is that I had altered the grid. I was directed to reset the grid to 100 mils, then it worked. It was a...
View ArticleForum Post: Re-using test benches by close loop with a variable
Hi all. Anyone could give me some hint about how close nets with a variable for different test benchs (a kind of cds_thru instance)?. In this way, I could use the same schematic to evaluate my...
View ArticleForum Post: can't reduce upper y extent
Hi In creating library part, if i change the Setup - -> Design Parameter - - > Design, the width and Height not able to modify, It is showing the following error. can't reduce upper y extent...
View ArticleForum Post: RE: Post place-and-route SDF back-annotation fails when using...
OK, maybe I solved myself. By TABbing some RTL Compiler synthesis commands I've found the syntax set_attribute hdl_flatten_complex_port true / With such an option all multi-dimension Verilog ports are...
View ArticleForum Post: Simulation Error in AMS sim. using remote-host
I simulated using AMS sim.; I used verilog code as digital block, and I import by virtuoso tool's function. Analog part was made by analog design. When I using AMS sim. in local, the simulation is done...
View ArticleForum Post: RE: Netlist Aborting in allegro PCB editor 16.5
If footprint contains " . " or / type of special character or name of footprint in .dra file is not same than this type of error occur also if one footprint name is in small and other (in orcad design...
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