Forum Post: RE: clock gating paths
Hi Bob,All, I am seeing a classic reverse case of above, in my design. No buffers are being added after ICG cells, and the ICG cell output is going to almost 500 flops directly resulting in huge skew...
View ArticleForum Post: RE: clock tree synthesis for clock gating
Hi Kari, In my case too, buffering didnt occur after the ICG cell, the ICG cell directly drives around 500 flops spread across the design, resulting in huge skew and latency. I didset the NoGating to...
View ArticleForum Post: [VIRTUOSO] Verilog netlister operation and pin order
Hi community I'd love to get rid of the following issues to enforce mixed analogue <> digital design simulation flow - is it possible to make the netlister generating a (system) verilog where...
View ArticleForum Post: RE: OrCad Capture add property from distributor
There are some details here parallel-systems.co.uk/orcadcip or talk to whoever you bought the software from. They can arrange a demo / let you know pricing.
View ArticleForum Post: RE: [VIRTUOSO] Verilog netlister operation and pin order
on enabling the 'explicit' option (which was promising) I see some instance be instantiated with explict portname .a(ww), some others NOT ... is this black magic?
View ArticleForum Post: Create and or Highlight Net Classes in Schematic
I have three questions that are related: 1. If I create net classes in Allegro using CM, is there a way to highlight these net classes in the schematic? 2. To speed creation of net classes in CM, is...
View ArticleForum Post: RE: hotfix not updating capture?
OK - thanks! Everything I see matches what you've described, as well, so I'll stop worrying about it :)
View ArticleForum Post: PCB Editor Dynamic Etch Shape Issue
I'm running into an odd problem. I have two pins on an SOIC-8 that are next to each other and tied to the same net. I'm trying to lay a dynamic shape over the two pins to connect them together along...
View ArticleForum Post: RE: OrCAD PCB Designer Professional 17.2: Rectangle vs. Rectangle...
Excellent response! Thank you for the help. I will definitely be saving it in my notes.
View ArticleForum Post: RE: PCB Editor Dynamic Etch Shape Issue
Solved my own problem. I had "Create pin void" set as inline with a 50 mils placing. Reducing the spacing fixed the issue.
View ArticleForum Post: RE: [VIRTUOSO] Verilog netlister operation and pin order
Hi, I believe that the explicit option does not apply to primitive devices, so the non-primitives will be netlisted explicitly, but the primitives use a default port order (something like outputs,...
View ArticleForum Post: RE: [VIRTUOSO] Verilog netlister operation and pin order
Primitives and UDP in Verilog can't be connected to by name, so Lawrence is correct. Also certain split bus configurations are always netlisted implicitly (by order) although I think we do it more...
View ArticleForum Post: *WARNING* hiDisplayForm:
Hello, I havn't understood this warning: WARNING* hiDisplayForm: cannot display blocking form Generateur_de_Para_Menu before initialization is complete. It is likely that a command in your .cdsinit...
View ArticleForum Post: ADEXL & Ocean Scripts
Hello everybody, I would like to use some ocean scripts to evaluate my simulation results. As Input signals I want to use other output results of ADE-XL (Output expressions). Is this possible in...
View ArticleForum Post: current in subckt cannot be saved, if the subckt is a PEX netlist...
Dear all, I have a test bench for just one inverter, as shown below: I want to run postlayout simulation for this inverter, specifically want to save the current flowing into the drain of T0. The...
View ArticleForum Post: RE: current in subckt cannot be saved, if the subckt is a PEX...
PS: I've verified the terminal name "D" in "/I0/XMT0/D" is the name used by the model file.
View ArticleForum Post: RE: current in subckt cannot be saved, if the subckt is a PEX...
And my Virtuoso version is IC6.1.7-64b.500.1
View ArticleForum Post: RE: current in subckt cannot be saved, if the subckt is a PEX...
If using a name which starts with a "/", you are specifying a schematic name (well, it doesn't have to be a schematic, but it's a name in Virtuoso's namespace). This needs to be mapped (during netlist...
View ArticleForum Post: RE: *WARNING* hiDisplayForm:
What it means is that you cannot display blocking forms during the .cdsinit file. This used to not raise a warning, and strange things would happen! You either need to add ?dontBlock t to the call to...
View ArticleForum Post: RE: Virtuoso: Comment Out
Hi Andrew, Thanks again for this reply. Unfortunately I have to go back to IC6.1.6-64b0500.11 now and hence use solution 11523164. Unfortunately it does not work; I do not see any visual...
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