Forum Post: how to custom abutted devices' poly to contact distance
Hello experts, I have quite a lot abutted devices in a long row. I'd like to expand the poly to contact distance so that they can pitch-match with other rows. I have an example snapshot here to...
View ArticleForum Post: UVM Register viewer
Hello all, I have implemented UVM Register model. I am able to check the values at the Interface level, but i cannot see the register values in the UVM Register viewer. Can anyone help me in fixing...
View ArticleForum Post: How to test a thyristor and distinguish an ordinary one and GTO ?
Hello~ all Nice to be here! I am a student who now learning the electronic course at college. And is there anyone can help me? Question one: I am checking a large high voltage device. It has a bunch of...
View ArticleForum Post: RE: UVM Register viewer
Hi Meghana. Did you compile your design with read access (xrun -access +r)? Without that, the simulator may have optimised the model such that it can't display the values. Also, make sure that your...
View ArticleForum Post: RE: Is it possible to do formal verification of firmware related...
Nothing is impossible :) but in practice this won't really work because formal doesn't work so well for very large numbers of clock cycles such as you would need for firmware execution. You might be...
View ArticleForum Post: RE: How to Setup Xcellium to run on Ubuntu
I very rarely see any Debian based Linux in use in ASIC companies, virtually everyone uses RedHat, and there's a cost to supporting different platforms (compute infrastructure to test each release,...
View ArticleForum Post: RE: Hierarchical design default pin placements
You cannot affect the default order of H-Pins assigned to a H-Block. In this specific case, since the signals follow a numerical sequence, you could use a Bus SigOut[0-127] / PwrOut[0-127] (or...
View ArticleForum Post: RE: PSS failing convergence on a SMPS model
Hi Andrew, Thanks for your feedback. I will file a Customer Support. If you don't mind, I will put you on CC. Br,
View ArticleForum Post: RE: Using custom VHDL library in cadence VHDL-AMS
Thanks a lot Andrew. I added the following lines in cds.lib:- softinclude /../xceliummain/19.03.007/tools.lnx86/inca/files/IEEE_vhdlams/cds.lib UNDEFINE ieee DEFINE ieee...
View ArticleForum Post: ENVLP Anaylsis Questions
I've few question regarding ENVLP analysis and wireless simulations within it. 1) Where can I find the actual values of important parameters after the analysis is finished..It seems that part of them...
View ArticleForum Post: RE: UVM Register viewer
Hi Steve, Thanks for your reply.. I have followed your feedback and still not able to see the register values like desired and mirrored in UVM Register viewer. Below given is the screen shot of...
View ArticleForum Post: RE: Issue with merging code coverage with different parameter...
As far as I'm aware there is no way to merge code coverage for different specialisations of a module.
View ArticleForum Post: Continue in line width while routing automatically
Hello guys, I was trying to find out if Allegro can do this but without any success. I am using version 16.6. I would like to know if Allegro can automatically continue in line width while router so I...
View ArticleForum Post: PCB Land pattern with multiple shapes
I am trying to make a PCB land pattern for an RF shield that is mounted using special clips. the clips are here: https://hollandshielding.com/PCB-shield-mounting-Ultra-tiny-clip-UTC...
View ArticleForum Post: RE: Is it possible to make aelEnvInterpret correctly evaluate the...
Andrew, I confirm it is exactly the case you described. Thank you so much! I have been going a so long journey(like trying to parse the expression by myself, removing pPar from CDF definition, ... etc)...
View ArticleForum Post: RE: Continue in line width while routing automatically
Just setup a few keyboard keys with your favorite trace widths. So then why you are routing a trace just hit your keys as you go. Here's an example of key that i have setup in my ENV. It assigns the...
View ArticleForum Post: RE: Continue in line width while routing automatically
I have found that when in routing mode (Allegro 16.6) if i set the Line Width (Options) to Constraint and I route from a Cline Seg then the route will continue at the same width. Hope this helps
View ArticleForum Post: RE: Using custom VHDL library in cadence VHDL-AMS
Also, I followed the steps given in The article VHDL parser error *F,DLUNNE: Can't find STANDARD at /tools/inca/files/STD . But, when I compiled (check and save) the dco entity, I got the following...
View ArticleForum Post: RE: PCB Land pattern with multiple shapes
If you don't need to connect to it (and will rely on the part making contact to the three pads) you can either make these mechanical pins so you then only have one pin the schematic. You can also place...
View ArticleForum Post: RE: How to Setup Xcellium to run on Ubuntu
I did get it working, the key missing lib was Linux Standard Base: lsb In the FPGA world, Ubuntu is most common and Xilinx tools work out of the box with Ubuntu. thanks, Andy
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