Andrew, First, we appreciate your time dedicated in this question. We inserted a Figure to exemplify our intentions. We are evaluating the reliability from part of the VDD line. We are assuming that VDD_1_8, for example, is the bottleneck. So, it is important to construct that table to evaluate our circuit. Thanks, Rafael
↧
Forum Post: RE: Measuring Layout Geometry
↧
Forum Post: RE: Measuring Layout Geometry
Rafael, OK, it looks as if you're trying to assess the potential electromigration failures using a rather simplistic approach. It's not much more than dumping out the dimensions of all the shapes you find on a particular net. This gives no heed as to whether there would actually be significant (or even any) current flow through a particular track; you might have a diminishing number of current sources or sinks further down the trunk and so it's OK to have smaller track widths there, but near the point at which the supply is connected, you might have much more current flowing through a particular track. Dealing with parallel tracks (both to the side or above/below) would also alter the assessment of whether you have a problem or not. Cadence already has tools to do this type of electromigration analysis (e.g. Voltus-Fi for signoff and Virtuoso Electrically Aware Design (EAD) for in-design, plus the older Virtuoso Power System (VPS)) which all use simulation to determine the current flows through the devices and can better solve the actual current flows through the tracks and be much more realistic than simply measuring the width and length of the tracks. These will deal with the fact that you have parallel paths and give you a much more accurate answer. Would it not make sense to use these tools instead? Kind Regards, Andrew.
↧
↧
Forum Post: Following up the subject of Cadence 16.6 and 17.2
Hi all, I am appreciate for all of your help. Since I am about to get cross over to the new 17.2 from 16.6 Do any of you have problem with the libraries, for example: Do you have any problem using lib created with 16.6 in 17.2 and via versa? If you do, please let me know what I have to watch for? How smooth is the 17.2 software going so far? Thank so much, Regards, TiBo
↧
Forum Post: RE: Following up the subject of Cadence 16.6 and 17.2
16.6 symbols will uprev on the fly when using them in 17.2. 17.2 is not(!) backward compatiable to 16.6. If you move a file to 17.2 you will not be able to open it with 16.6. To prevent any accidental saves of 16.6 data that may have been opened with 17.2 use the variable that was introduced with the 17.2 QIR1 (S004)release uprev_answer: If set, does not display the major release design uprev warning but provides the default answer. If value is "no" then a user is not able to open designs from older releases without using another method. This disables the noconfirm_uprev environment variable.
↧
Forum Post: RE: Can I draw a reference line in virtuoso?
How about this? /* CCFenterRefLine.il Author A.D.Beckett Group Custom IC (UK), Cadence Design Systems Ltd. Language SKILL Date Dec 02, 2016 Modified By Example of a enter function to prompt you to enter two points, and then to create a marker as the result. Might want to use: pteSetVisible("Markers" t "Objects") to ensure they are visible. Call CCFenterRefLine() to prompt the user to create the marker line. *************************************************** SCCS Info: @(#) CCFenterRefLine.il 12/02/16.10:03:27 1.1 */ procedure (CCFenterRefLineCB(wid ok points) let ((cv) when (ok && wid cv= geGetEditCellView (wid) dbCreateMarker (cv "Reference Line" "CCFenterRefLine" points nil t nil ) ) ) ) procedure (CCFenterRefLine() enterLine ( ?prompts list ( "Enter first point" "Enter second point" ) ?wantPoints 2 ?doneProc "CCFenterRefLineCB" ?cursor hicTCross ;hicCreateRulerEdge ) )
↧
↧
Forum Post: RE: Why can't I mark net?
There are a couple of solutions on the support site which cover this. Solutions 20412000 and 20224524 . The gist of these is that you have a markNetOptions file which has either a syntax error in or is referring to a non-existent layer. Yes, there should be a better error reporting mechanism (this may have improved in more recent versions, but there's also an outstanding CCR on this too - you didn't mention which version you're using, which is always an important piece of information). Look for the file .cadence/dfII/markNet/ cellTechLib /markNetOptions where cellTechLib is the name of your technology library - this .cadence dir could exist in a number of different places - e.g. your working dir, your home dir a site wide directory ($CDS_SITE) and various others - try using "cdswhich .cadence/dfII/markNet" in the UNIX terminal to find candidate directories. You might want to rename the file and recreate the options from the Mark Net form rather than trying to fix it up yourself. Regards, Andrew.
↧
Forum Post: RE: Transient noise analysis, long run or multiple runs
Hi Manuel, You shouldn't have to specify the seed - but the multiple runs does indeed ensure that you have a different sequence of random numbers for each run. If the circuit is settled and doesn't have memory effects that last longer than a cycle then they should be equivalent statistically - each cycle should represent a sequence of different random numbers than the others according to the distribution controlled by the noise source parameters. The benefit of multiple runs is primarily that you could do them in parallel rather than sequentially. Regards, Andrew.
↧
Forum Post: Got Stuck in Harmonic Balance Analysis
Hi all, Recently I needed to run a lot of hb analyses but always got stuck in the processing. Not saying hb would not work, but it generally takes much more time than I expected. So I looked into the output log while monitoring the CPU utilization of spectre. Here is the problem I found. DC and AC analyses were run before HB, and both seemed to work well with a CPU utilization of around 400%. So I thought computing resources were abundant and thus expected HB analysis to utilize more computing resources to move faster. However, it turned out HB got stuck between "Important HB parameters" and "initial residual" for plenty of hours, while the CPU utilization fell down to 100% or less. It's like: Important HB parameters: RelTol = 1.00e-3 abstol(I) = 1.00e-12 A abstol(V) = 1.00e-6 V residualtol =1.00e+00 lteration = 3.50e+00 steadyration =1.00e+00 maxperiods =100 ( Here spectre got stuck for plenty of hours, not even bother to move! ) **initial residue** I am not sure whether or not it's common; Worse, no idea attained after I consulted the local Cadence AE. She checked my settings and said there was nothing wrong. "Maybe it has something to do with the host machine", she said. So does anyone know what spectre is doing where it gets stuck in my case? Any solutions? By the way, I am using IC6.1.6-64b.500.10 and spectre 15.1.0.345.isr2. Thanks a lot! Marco 2016.12.02
↧
Forum Post: RE: Got Stuck in Harmonic Balance Analysis
Hi Marco, I don't think there's really enough information to work on here. Please contact customer support so that we can follow this through formally - we need to see the log files, and may well need access to the testcase, and probably get an RF specialist looking at this. Without knowing far more about the circuit, I doubt I could answer this via the forums - the same would be true of other AEs who work in this space. Kind Regards, Andrew.
↧
↧
Forum Post: RE: Saving/Importing/Exporting the ADE Results
You didn't say which version or which flavour of ADE you're using. Anyway, here's some guidance of general principles: In ADE L or ADE Explorer (or ADE in IC5141) when you re-open you can do Results->Select to load in the last results you saved. You can also do Results->Save to save away to a different name and then use Results->Select to reference any of the saved previous results. This saves the waveform data plus the netlists and so on. You can also use all the plotting capability having re-loaded the results again (including the "plot outputs" icon in the bottom right corner. In ADE XL or ADE Assembler, the default behaviour is to save up to the last 10 set of simulation results. You can see these in the history tab in the data view assistant in ADE XL/Assembler. You can rename these history points, lock them (using Right Mouse->Lock) to stop them being deleted or auto-deleted, and also do Right Mouse->View Results to load them back in again in a subsequent ADE XL/Assembler session. Hope that helps. Regards, Andrew.
↧
Forum Post: RE: Got Stuck in Harmonic Balance Analysis
Hi Andrew, Thanks for your reply. I guess that's all we can do here. As long as the analysis can finally disgorge some results, no matter how long it would take, we would choose to put up with it and then forget it. Involvement of different guys from two companies may be a much larger project than a single simulation. I posted out the issue just hoping to see whether or not you guys may have a clue, since you guys look sooooooo erudite, not really depending on a direct solution. You have done much more than I expected and sincerely thank you sir. Maybe sometime later I would somehow resolve the problem, in which case I would post it here. Regards, Marco.
↧
Forum Post: RE: Got Stuck in Harmonic Balance Analysis
Marco, Not necessarily - it may just be having a webex with an expert in this area can pinpoint a setup problem which is exacerbating the problem - it's very hard to know without seeing at least the log file and the analysis statements in the log file. It may not be a big project to figure this out... Regards, Andrew.
↧
Forum Post: How to turn off automatic dimming in layout
Hello, I would like to ask you, how to turn off the automatic dimming of layout enviromend (Options->Display->Automatic Dimming) using .cdsinit, because this dimming is turned on by default. I have already tried this commands (below), but no one of them worked and automatic dimming is still turned on: envSetVal("layout" "dimmingAutoEnabled" 'boolean nil) envSetVal("graphic" "dimmingAutoEnabled" 'boolean nil) envSetVal("layout" "dimmingIntensity" 'int 0) envSetVal("graphic" "dimmingIntensity" 'int 0) Thanks, Matej.
↧
↧
Forum Post: RE: Got Stuck in Harmonic Balance Analysis
Andrew, The thing is the company where I am working has stringent information security polices. Just imagine that even download of results files from the servers to the local need permission from your manager, and some guys are always watching you. So I seriously doubt they would permit me to do what you kindly proposed. Regards, Marco.
↧
Forum Post: ADE-XL plot graphs by reading data from the database
Dear all, I have an ADE-XL with several tests and I would like to plot specific waveforms of each test, which have been specified by the user. I was wondering if it is possible to access the database of each run and get the data. A different question but related When I select a given test on ADE-XL, let's say STB I get the following command in the log file: _axlTestFilterChanged(axlOutputsForm4->axlOutputsWidget4 "'(\"STB\")") Cadence appends a number to the commands, in this case 4. This seems to be different from one ADE-XL session to another. So, when coding, how can I get this number ? Best regards, Pedro
↧
Forum Post: find out which SKILL function is called in the background
I have a schematic , where if I select any of the instance and press Q (Edit Object properties) , some function is getting called (Internal customization) and it does the check n save of that schematic. I am trying to figure out which function is called. I have tried setting sstatus debugMode t and sstatus stacktrace t , also enabled all the "log filters" but that didn't help . Is there any other pointers which I can try .
↧
Forum Post: RE: find out which SKILL function is called in the background
The brute force way would be to use trace(t) . I would probably adopt some more refined tracing myself, but then again I'd probably need to understand exactly at which step it occurred. I might start with tracing the schematic extraction type functions: trace(schExtractConn schCheck) and then if these show up as being triggered, I might then set breakpoints on them (using breakpt), invoking the command that triggers it, and then typing "where" in the CIW to find out the stack trace at the point the debugger has kicked in (type continue() to continue from the breakpoint). Regards, Andrew.
↧
↧
Forum Post: RE: MMSIM Issue with IC5141
Thanks Andrew for your reply. Once i run the scripts,it loads CIW but there error reads: "cds_root: the tool is not available on lnx86 platform. unable to find cadence installation" I am not able to open library editor. but i can open my cell views and things but cannot run simulations.
↧
Forum Post: RE: Using the Virtuoso autorouter: routing grid
Hi, The routing pitches are determined by a lookup mechanism that starts with the settings that you have in your Wire Editor environment and ends with settings in the Process Rule Override. (PRO have the highest priority) Because I have no access to your data I will make some guesses (based on a typical setup): You have a Constraint Group called "LEFDefaultRouteSpec" defined in your technology library. This contains the routing grid and offset definitions You have loaded this constraint in your Wire Assistant. You have setup route to "routing grid" and nothing happens........:( Here is one last suggestion. If this doesn't work we need to ask you to contact customer support. Go to options->Editor Look at the section "wire editing (wire)" Make sure that the Default Wire Constraint Group "LEFDefaultRouteSpec" is specified. Try routing again. Let us know if this works. Regards Colin
↧
Forum Post: RE: Saving/Importing/Exporting the ADE Results
Dear Andrew You made it easy. I am using ADE version IC6.1.5.5000.16.2. Many many thanks. Regards
↧