You may need to adjust the placement grid to get "exact" alignment (Setup - Grids - Non-Etch) but check your preferences as I said earlier to remove component origin. For the ratsnest, if a no rat property is On you won't see rats for that net. If you don't have this property then you will see a rat BUT if you also have a Voltage Property assigned the rat will be displayed as a square with a cross in the middle (GND in your screenshot). If you remove the Voltage property you will see point to point rats.
↧
Forum Post: RE: How to move component so that the pad aligns to the pad of another component (like Altium does)
↧
Forum Post: RE: orcad capture 17.2: Bus has no name and therefore defines no signals
So buses must have the same netname type A0 - A7, DQ0 - DQ7, MSB...LSB based on the same name, and the BUS must have the same name A[0-7]. DQ[0-7]. If you want to use different netnames then create a Netgroup. There's a video on netgroups www.youtube.com/watch
↧
↧
Forum Post: RE: Global variable sweep in Monte carlo analysis
HI Andrew, there is one particular net where the matrix calculations seem to be facing an issue. Zero diagonal found in Jacobian at `net0130' and `net0130'. are there any diagnostics that i can try around this node ?
↧
Forum Post: RE: Assura and Quantus options
thanks Andrew, I ran " Assura -> Run Quantus QRC" which ran successfully. But i cant locate any dspf / spef file anywhere. I am trying to run EMIR So what am i missing to be able to generate files required (i think DSPF) for running Voltus-FI ?
↧
Forum Post: RE: Assura and Quantus options
Did you set the Output on the Setup tab to "Transistor Dspf"? That's where you specify the output file... Regards, Andrew.
↧
↧
Forum Post: RE: Global variable sweep in Monte carlo analysis
That may suggest that the node is floating (or near floating). Andrew.
↧
Forum Post: RE: Output expressions containing variables and parameters not executed when using ADE XL
Hello all, I am having the same issue, but it is not solved. I created the following expressions on the ADE Assembler outputs: t1 --> VAR("retraso") t2 --> (VAR("retraso") + (VAR("step"))) retraso and step are design variables and they are properly defined. *Error* ("plus" 0 t nil ("*Error* plus: can't handle (nil + nil)")) *Error* Evaluating expression ((VAR("retraso") + VAR("step"))). *Error* ("eval" 0 t nil ("*Error* eval: not a function" VAR("step"))) Thanks in advance
↧
Forum Post: RE: Output expressions containing variables and parameters not executed when using ADE XL
Would have been better to start a new thread (As the forum guidelines suggest), but anyway it would be useful to know: Which IC subversion are you using (Help->About will tell you) Are there global variables with the same name defined, or just design variables under the test? Are the global variables enabled if so? Are the output expressions using VAR for the same test where the design variables are defined? Andrew.
↧
Forum Post: RE: Output expressions containing variables and parameters not executed when using ADE XL
Hello Andrew, 1- Cadence IC6.1.7-64b-500.15 2-No global variables, just a few of design variables 3- I have only one test, so all the output expressions are belonging to the same test. Thanks for the quick answer
↧
↧
Forum Post: Get hierarchical shape net names for the current cellview
How to get the net name of an Instance with Skill in Virtuoso Layout in the context of the current cellview? I tried instance->master->shapes Then select a shape and readout: shape->net->name But now the net name is in context of the instance or Pcell instance and not the net name corresponding in the cellview. Is there a way to get the in the cellview given connectivity for a shape inside an instance or pcell? Thank you for your responses
↧
Forum Post: schNetExprEvalNames issue inside bus-like instance
Hello, I have a strange problem with some code I am maintaining (although did not write myself). The code attempts to get the top most name of nets connected to pins with inherited connections. For this it uses schNetExprEvalNames followed by geGetAdjustedPath. schNetExprEvalNames seems to have a bug or issue if on the path there is a instance like I . I have two placements of a cell, once with bus once without, and lower in the hierarchy I have a device with an inherited pin /TOP/I11/i_R/I0/I18/I3/I4/I1/ntrans11 is one /TOP/I11/i_R/I0/I18/I1 /I4/I1/ntrans11 is the other. the inherited term we have dbGetTermNetExpr(term) -> "[@hSup:%:VSS!]" what the code does is this, some differences in red schNetExprEvalNames( ds list(/TOP/I11/i_R/I0/I18 / I3 /I4/I1/ntrans11 ) ?listCellView t) which returns a list including the net ((("/TOP/I11/i_RACS2/I0/I18 / I3 /I4/GND"1 1 (("lib" "cell" "view" "lSup" "VSS!" 1 ) ) nil ) ) ) after which geGetAdjustedPath(designWindow "/TOP/I11/i_RACS2/I0/I18/ I3 /I4/GND") returns "/TOP/I11/vss_r_net" but on the second instance: schNetExprEvalNames( ds list(/TOP/I11/i_R/I0/I18/ I1 /I4/I1/ntrans11 ) ?listCellView t) which returns a list including the net ((("/TOP/I11/i_RACS2/I0/I18 / I1 /I4/GND"1 1 (("lib" "cell" "view" "lSup" "VSS!" 1 ) ) nil ) ) ) I1 does not exist in the schematic, have no idea where the proc gets it. And off course the net does not exists. what I did notice is if I skip schNetExprEvalNames and go to the level of the transistor and apply geGetAdjustedPath directly, I get the correct net geGetAdjustedPath(designWindow "/TOP/I11/i_RACS2/I0/I18/ I3 /I4/ I1/VSS! ") returns "/TOP/I11/vss_r_net" geGetAdjustedPath(designWindow "/TOP/I11/i_RACS2/I0/I18/ I1 /I4/ I1/VSS! ") returns "/TOP/I11/vss_r_net" So my question is: is there a reason I absolutely need schNetExprEvalNames or can I be confident that using geGetAdjustedPath gets me the results I want? Are there situations when only geGetAdjustedPath gives bad results? Thank you. Regards, Radu
↧
Forum Post: RE: Get hierarchical shape net names for the current cellview
There is not "one" single net an instance is on - an instance is usually connected to more than just one net - here's how you get at the net names: instance->instTerms~>net~>name
↧
Forum Post: RE: Get hierarchical shape net names for the current cellview
Ok, but is there a way to get the corresponding net name from a shape inside the instance?
↧
↧
Forum Post: RE: How do I move my entire project in PCB Designer
The work space is easy to change if for some reason your design is right up to the edge of the work space. Just go to "setup/Design Parameter Editor, Pick the "design tab" then type into the extents fields to change your design window. Make the width bigger than what you have currently. Example lets say you had W500xH500 in mm. Change it to W1000xH1000. Then change the Left X and the Lower Y to exactly half of the W and H. So you should type in -500X Y-500. then Hit OK. Your entire design will re-center with room to spare. To move your entire design you just need to turn on the correct filter switches and have all your layers turned on (top,bottom, internals). 1. Make sure you are in the general edit mode. 2. Then turn on Symbols, Pins, Vias, Clines and shapes. 3. Window around your design to select everything. Right click them move. To move to a precise location - at the bottom of your screen, switch "A" to "R" Then after right click move and everything is highlighted. Go to the option window. Make "Point" set to "User pick" pick the highlighted items again to re-position the mouse to a point of your own choosing. Notice the design coordinates change to zero/zero just prior to moving you design. Hit the "P" and type in the new location to drop your design to the precise location. Thats it.-- Cheers
↧
Forum Post: RE: Get hierarchical shape net names for the current cellview
Well, it depends on whether the shape has got connectivity or not - many shapes inside PCells will not have connectivity - typically only the pins have connectivity. Assuming the shape does have connectivity, you're only going to get the higher level net name if it's actually a shape on the same net as the terminal (terminal is the logical, pin is the physical). So for a shape inside the PCell, knowing shape~>net~>terminal~>name, and then if you looked over instance~>instTerms~>name for the same terminal name, you could look at the instance~>instTerms~>net~>name to find the corresponding net at the level above. Sorry if that was a bit poorly described - it's hard to know precisely what you're doing in terms of processing the design. Andrew.
↧
Forum Post: RE: Get hierarchical shape net names for the current cellview
master = instance->master (foreach mapcar instTerm instance->instTerms (list instTerm~>name (setof shape master~>shapes shape~>net~>name==instTerm~>term~>net~>name)) )
↧
Forum Post: RE: orcad capture 17.2: Bus has no name and therefore defines no signals
Thanks Steve. That solved it. Frank
↧
↧
Forum Post: RE: Output expressions containing variables and parameters not executed when using ADE XL
Hi Alberto, I just tried this in the same sub-version as you, and it worked fine for me. I suspect there's some subtle problem in the setup that I can't see from your description. The best thing would be to contact customer support and then we can look at your data? Regards, Andrew.
↧
Forum Post: RE: rfTlineLib sbend
David, This looks like an oversight in the rfTlineLib implementation. The underlying component in spectre seems to be limited to within -90 and 90, but both sbend and mbend have checks to limit the angle between 0 and 90. You should contact customer support to request that this is fixed. Regards, Andrew.
↧
Forum Post: Warninh: Symbol not found
Before we get into this, let me point out that I am a newbie to Allegro/Orcad PCB so please forgive me if I am making a rookie mistake. I am having a torrid time trying to bring custom footprints into Orcad PCB generated by Ultra Librarian online library. So far: 1) Have set the psmpath, devpath and padpath User Preference paths to point to directory in which the new footprints are located. 2) Have attempted to copy the footprints into the source drive (although I am not quite sure which directory this should be, there appear to be several source library directories with similar files) 3) Rebuild the netlist several times 4) ensured that all my files are in the same directory (pointed to by variables identified in pint (1) above) Any pointers would be gratefully received.
↧