can you suggest where can I find pcell code of any diode?? Thanks and Regards Raegaan
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Forum Post: RE: pcell
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Forum Post: RE: pcell
I did a quick search and couldn't find open source code for this, sorry. Andrew.
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Forum Post: LSSP Simulation for Floated RF Port is Reliable?
Hi, Hope you are doing well and stay fine. I am working on designing cross-coupled or differential RF Rectifiers using Cadence. Rectifiers are highly non-linear devices that cannot be charecterized by SP analysis, so we have to use LSSP simulation instead. I have tried finding the magnitude and phase and convert it to Z parameters to be able to match the input, I use the complex conjugate value of the simulated valuein the port to be able to see if the LSSP shows the port is matched or not, but the new results does not show the matching and the results are even worse. Therefore the question arises here that can we rely on the LSSP simulations if the port is floated like what I have in the attached schematic? How the port calculates the S11?
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Forum Post: RE: Step model "skinning" export in 17.4?
Goal: create a single SW part from an Allegro Step assembly that won't get broken down into a couple hundred individual *.SLDPRT files having filenames the Mechanical engineers aren't familiar with. Import the Step model into Solidworks. File> Save As> set the filter to Part (*.prt, *.sldpart), click the radio button "Exterior Faces". Interesting is it keeps the color detail of the part step models but it is now a single object that should be faster for the mechanical engineers to use, so they won't complain as much. O_o
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Forum Post: RE: pcell
ok thanks Andrew Regards raegaan
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Forum Post: RE: Subthreshold Standard Cells Characterization by Liberate
Hi Guangjun, Thank you for your prompt reply. 1. you are right, a power pin cannot be 0V. For VDD I don't set 0V, however for Nwell one can do body biasing and set Nwell to a voltage, e.g. higer that VDD (to increase Vth) or lower than VDD (to decrease Vth). I'm not using SOI technology. 2. At the beginning I used set_vdd VDD $VDD and also set_vdd VDDNW $VDDNW and set_gnd VSS 0. I was not aware of using '-no_model', thanks for your suggestion. 3. Affter causing issue with VDDNW I tried with these two commands from Liberate Doc. VDDNW is the forth device port (in schematic), but not presented in layout. Now I use the command set_vdd -type nwell VDDNW 0 4. tapcell is not part of cells but also a separated cell. 5. muliple supplies could be interessting, e.g. for levelshifter if the circuit uses both low and high voltage. However for a cell with single power supply I think one could put different values for supply (here VDD) in corner-lists, which I plan to do. However for each 'island' on the chip level there is only one VDD. Please correct me if I'm wrong. Maybe, do you mean I should set_pin_vdd for VDDNW since this is an additional power line? Indeed on the chip top level there should be VSS, VDD and VDDNW lines. I repeat my question of last post: 1. For postlayout simulation I generated for each cells (inclusive tapcell) parasitics. Should I do extraction for each cell manually again or Liberate does this job? - in cell_list there are only the name of cells (not tapcell) Just I run characterization with set_vdd -type nwell VDDNW 0 . At least it takes time! Starting on grid with 10 cpus ---- Template Generation start ---- ---- Template Generation done ---- -- Characterization Summary -- 2 warnings 117 errors Starting on grid with 10 cpus ---- Characterization start ---- ---- Characterization done ---- -- Characterization Summary -- 1 warnings 1 errors Starting on grid with 2 cpus ---- Write library start ---- ---- Write library done ---- -- Write library Summary -- 2 warnings 1 errors 0 monotonicity warnings Starting on grid with 2 cpus ---- Write CCS library start ---- ---- Write CCS library done ---- -- Write CCS library Summary -- 2 warnings 1 errors 0 monotonicity warnings Starting on grid with 2 cpus ---- Post-processing start ---- In char.log there is one ERROR (LIB-19): Failed to read file (file=/....... .template.tcl": no such file or directory while executing All 117 errors are due to the 'permission' of cells layout.oa, which are automatically set to -rw-rw----. Maybe, should it be changed to rwx-rw-r--? ERROR (LIB-902): Failed to open file '/.../AN2d1.sp' for read. Check directory/file paths and permissions and rerun. ... There is also a warning: WARNING (LIB-988): (set_vdd): Vdd 'VDDNW' is driven to 0.0 volts. It is normal for ground nets to be set to 0V. Use the set_gnd command instead of set_vdd to clear this message. However I want this pin to be selectable for different values, e.g. 0, VDD/2 and VDD for desired speed or leakage performance Maybe the values of differemt VDDNW should be given in corner-list, like VDD? The same error in write_ccs and write_nldm: Maybe, is this a consequential error? ERROR (LIB-195): (read_ldb): Unable to read the ldb '/xxx.ldb'. Check whether the specified file path is correct and the required access privileges exist on the file, and rerun. WARNING (LIB-193): (read_ldb): Future characterization and modelling commands will be skipped because of the previous error. Correct all Tcl errors and rerun. I will correct it and report you. In meantime thanks a lot for your help! Kind regards BarPouy
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Forum Post: RE: Subthreshold Standard Cells Characterization by Liberate
again, you can not set a vdd to "0" using set_vdd. if it is "0", use set_gnd. 1. if the content of tap cell is required for the cell to behave as expected, then it is part of the cell, and should be extracted as part of cell in the post layout netlist. 2. liberate does not work on layout data (layout.oa), it uses netlist. not sure why this is a question of issue. 3. yes, different VDDNW values should be handled as different corners. 4. Failed to read file (file=/....... .template.tcl"-- seems the path/file is not correctly defined in your scripts. 5. the rest does not make sense, since your run fails at the very beginning. Guangjun
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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
Dear Andrew, I have the same problems as he does. After changing the kernel file(.cshrc, .bashrc), and I re-run it. Then, I can't access to virtuoso anymore. (btw, I still use ICADV12.3) The terminal pops up the following message: ntugiee@MK_CentOS[/home/ntugiee]#ERROR (DB-320001): Failed to check out the 'Cadence(R) Design Framework II' license. Run 'lmstat -f 111' command to check the license usage status. Contact Cadence Customer Support for assistance. lmstat -f 111 lmstat - Copyright (c) 1989-2015 Flexera Software LLC. All Rights Reserved. Flexible License Manager status on Mon 5/18/2020 22:48 Error getting status: No SERVER lines in license file. (-13,66) [1] + Exit 111 virtuoso and I check the above issues you raise, I find the network is unreachable after I type a command," ping 8.8.8.8", to check. But I double-check the network cable line of my host computer, and it solidly links to my computer, which means it can link to Cadence with the right IP. Therefore, I would like to ask if it is the network problem contributing to can't access to virtuoso. If it is, how to solve it. Thanks in advance. Appreciate Daniel
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Forum Post: RE: pcell
you may find SKILL code for some pcells here, /tools/dfII/samples/ROD/rodPcells/components/. A diode pcell can be coded similarly to eb junction of a BJT. Guangjun
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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
What is $CDS_LIC_FILE set to? Do you have $LM_LICENSE_FILE set? What about $CDS_LIC_ONLY? To be honest, this is best handled by customer support so that you can get a response in a timely fashion (I'm a bit busy with the day job today). Andrew.
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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
Dear Andrew, Many thanks for your rapid reply. Wish you all the best in your work. You are such a kind person. I will go to consult with customer support. Thanks btw, I couldn't find CDS_LIC_FILE, LM_LICENSE_FILE, and CDS_LIC_ONLY under my file. Furthermore, I tried again to type "source .cshrc" in the terminal and then ran virtuoso. Even worse, it popped up the following message. ntugiee@MK_CentOS[/home/ntugiee]#ERROR (DB-320001): Failed to check out the 'Cadence(R) Design Framework II' license. Run 'lmstat -f 111' command to check the license usage status. Contact Cadence Customer Support for assistance. lmstat -f 111 lmstat - Copyright (c) 1989-2008 Acresso Software Inc. All Rights Reserved. Flexible License Manager status on Tue 5/19/2020 00:22 Error getting status: Cannot find license file. (-1,71) [1] + Exit 111 virtuoso I think I really have to go for help. Thanks, Andrew Have a nice day Daniel
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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
So if you type: env | grep LIC does it output anything in the shell? It may be that you have not got any environment variables defined to tell it where the license server is. I suspect you're running a pretty ancient version, because of the date on the lmstat command (Acresso became Flexera in 2009). Andrew.
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Forum Post: RE: Too many Point Sweeps (>1 M) for ADE XL to handle
Hi Andrew, I am using IC6.1.6.500.14 Thanks! Brayden
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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
Dear Andrew, Thanks for your rapid reply again. Sorry for bothering your day job. Here is the message report. ntugiee@MK_CentOS[/home/ntugiee]#env|grep LIC LM_LICENSE_FILE=/usr/cad/synopsys/license/sx_2010_license.dat CDS_LIC_FILE=/usr/cad/cadence/license/full_license.dat:/usr/cad/cadence/license/mmsim10_license.dat MGLS_LICENSE_FILE=/usr/cad/mentor/license/calibre2011_license.dat I can find sx_2010_license.dat and calibre2011_license.dat under the right path. However, I even couldn't find the "license" file under the /usr/cad/cadence. I would like to ask if I should make the directory which names license and then download that file, full_license.dat, on Cadence. Or I should download the whole package, ICADV12.3, to get that file. Thanks a lot. You truly a kind man. Appreciate Daniel
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Forum Post: RE: Assura RCX fails
Yes It is clean. by the way, I just tried to remove the capacitors from the circuit, and after modifying the chematic as well, the DRC, LVS and RCX work successfully. So, what is the potential problem? I have to work with these capacitors in my design.
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Forum Post: RE: Too many Point Sweeps (>1 M) for ADE XL to handle
I just tried in that version. I created a bunch of variables (with 6 sweep points in each). If they are not grouped, I get this: There's no highlighting of the variables - the background is white, and you get the huge number of point sweeps. If I then select and use the right mouse button menu: Having done this, you see the grouped variables highlighted in the same colour (note the bottom variable is not grouped): As you can see, the number of point sweeps is dropped. However, your UI showed something about a submit point. So, if you go to the "gear" icon next to the run mode, and then click on this Override Active Setup: If you do that, it then ignores the group as parametric set (the sweeps are defined in the "Specify Points" UI). Note that the same problem occurs in the latest versions too - if you override the active setup from the Single Run, Sweeps and Corners options form. So go to that form, and turn off the "Override Active Setup". If you really need to override the setup, you can use the "Setup States" to save a set of variable sweep settings, and then load different Setup States to switch between them. Regards, Andrew.
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Forum Post: RE: Assura RCX fails
Did you try using Quantus QRC (since Assura RCX is not supported)? Perhaps the decks are not set up to support these capacitors? Very hard to debug without seeing the data. Andrew.
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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
You won't get the license file by downloading the software again - the license files are shipped separately as they are unique per customer. You need to contact your account team (or University program) to ensure you have the license file (and the license server needs to be set up too). Explaining all of this is beyond the scope of these forums, to be honest as I don't know anything about what products you have (or even who you are). So customer support is the right channel. Regards, Andrew.
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Forum Post: Setting up a bussed differential pair (DDR CLK)
Can anyone tell me how to properly define a bussed differential pair so the static phase can be tuned for each individual segment? The DDR CLK pair runs from FPGA thru five DDR components. After routing the CLK pair, constraint manager automatically defines some random set of pin pairs. I cannot create pin pairs or delete any of these pairs.
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Forum Post: RE: Setting up a bussed differential pair (DDR CLK)
FYI - running 17.2 with hotfix 63
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