Sorry davidJHutchins but the 3rd line down on my simple script (this is taken from a larger script but shortened here to show what is broken in as short a script as possible) the line saying axlGetSelSet(axlSingleSelectName( "NET" net1 )) highlights the net. I also tried it your way and it still doesnt work The full script is running in a gui and what it does is select the net and all the components hanging from that net and then does a 3d representation
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Forum Post: RE: skill fails for 3d
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Forum Post: RE: ADE Ldesign with complex variable
Hi Frank This solution doesn't seem to work in ADE-L when I use it to assign a string to a variable. For example: leak=0 moscor=(leak==1? "top_ff" : "top_ss") I get a syntax error: Cannot run the simulation because syntax error `Unexpected quoted string ""top_ff"' was encountered at line 9, column 38. Is there any other way to assign a conditional string to a variable in ADE-L? I use ICADVM 18.1.500. Thank You -Nanda
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Forum Post: RE: Create object then use leHiMove or leHiCopy
Found it I use preXy and it works
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Forum Post: connecting to odd shape pad
I am trying to connect to the ground pin on the Rosenberger 19S101-40ML5 SMO connector shown in the image. I have created the footprint using shape symbols. Now, the center of the GND pin is not metalized. I want to connect the GND VIA to one edge (top edge here) of the GND pin. How do i do that? I can recenter the shape symbol so that the center falls at the center of the metalized portion on the top edge, but then if i want to connect to the left or right edges in another instance i have to recreate the symbol with a different shape symbol (center of the pin moved again), i guess. Is there a straight forward way to do this in OrCAD, so that i can just snap to any metalized part of a pin?
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Forum Post: RE: connecting to odd shape pad
Here is the image
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Forum Post: RE: connecting to odd shape pad
Where the "G" is in RF_GND going into the ground shape, I move the pin origin there, not at the center of your SSM. Allegro expects the cline to end at the pin origin. In this case, the pin origin is where no copper should be. I may have trimmed the cline back to get the board out but didn't have a fully valid netlist. (by the way, the width of your signal pin directs the trace width you need to match 50 ohms. This sticks out as an impedance mismatch. Your microstrip width really needs to match the width of the pad. See the connector datasheet.)
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Forum Post: RE: connecting to odd shape pad
We use the same part in High Frequency ATE boards. The outer pin should be a full pad connect, note the copper voids for thermal relief and the pin origin must be within the copper shape of the outer pin. The center area must be free of copper, or you will get unwanted parasitic capacitance to the signal pin. The route from the pin is a co planar controlled impedance. Good luck. BTW the impedance in this case is 90 Ohm - my bad, I just double checked the impedance. RFinley is correct, 50Ohm.
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Forum Post: RE: Running 17.2 and 17.4 on the same system.
Could we somehow change the default version associated to .mcm or .brd files? it seems like changing the CDSROOT system variable does not help. Thanks!
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Forum Post: RE: Running 17.2 and 17.4 on the same system.
I've always done that by selecting a BRD file, then >OpenWith >Choose Another App. Don't forget to review the checkbox if you want to change the association with the filename extension. For reference, here are the paths. C:\Cadence\SPB_16.6\tools\pcb\bin\allegro.exe C:\Cadence\SPB_17.2\tools\bin\allegro.exe C:\Cadence\SPB_17.4\tools\bin\allegro.exe
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Forum Post: RE: Edit in place to specific instance
Hi Andrew, I used to get a list for the hierarchical path to a particular shape by clicking on it after invoking leHiEditInPlace() - this allowed me to get an idea of where that shape sits throughout the hierarchy and gave me the ability to select which level I want to descend into from that list. However, I'm not seeing this in my new team's environment. Was this only available in older versions, or is there an option that I need to tweak somewhere? I'm using ICADVM18.1-64b.NY_ISR10_SUPPORT.2 Thanks, Fari
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Forum Post: RE: connecting to odd shape pad
Radio is mostly 50 ohms. Risky assumptions. My impression is high-speed digital is around 100 ohms. Kudos on coplanar waveguide. We usually pull ground away and do microstrip.
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Forum Post: RE: connecting to odd shape pad
thank you for the info, and the bonus tips. Our application is low frequency (30 MHz) and uses lumped element matching, we do not need coplanar waveguides or microstrips, the traces are very short compared to the wavelength at 30 MHz.
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Forum Post: How to define inital starting size for dockable window form
I'm creating a GUI in cadence 6.1.7.500.22 and am having trouble defining the initial docked size. I've tryed using ?dockSizeHint ?minimumSizeHint inside of the hiCreateDockWindow command as well as ?minSize inside of hiCreateLayoutForm but nothing seems to work. Everything else about the gui is performing as expected but this last issue has be stumped. Any help would be greatly appreciated! Basic outline: formName= gensym ( 'JFmtForm ) ;All the gui related fields here and then.. JFmtForm= hiCreateLayoutForm ( formName "Marty Toggles 2.0" JFmtTopFormVertBox ;?minSize list(1000 1000) ?buttonLayout 'OKCancel ?unmapAfterCB t ) cw= hiGetCurrentWindow ( ) swin = hiGetSessionWindow (cw ) dockForm = hiCreateDockWindow ( ?appType "Docked Form" ?widgetType "form" ?handle 'JFmartyToggles2 ?title strcat ( "Marty Toggles 2.0 - " tech ) ?form JFmtForm ;?dockSizeHint list(1000 1000) ;?floatSizeHint list(1000 1000) ;?minimumSizeHint list(1000 1000) ) myDock = hiDockWindow ( ?window dockForm ?session swin ?side 'right )
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Forum Post: RE: Part Editor in Capture 17.4 S009
if the pins are marked and you click on them, a black cross appears. Then you can move the pins. The cross does not always appear and the selected pins are free again
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Forum Post: RE: Edit in place to specific instance
Hi Fari, There's a (currently private) cdsenv variable to control this. I'm not sure why it's still undocumented, so I will ask that when I'm back at work next week. Andrew.
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Forum Post: RE: Port Noise Error?
Please contact customer support - this seems to be something peculiar to the test case you have here as I cannot reproduce it, and cannot see anything in the log file which gives any clues. Even if I explicitly disable the noise from the port (e.g. using the noiseoff_inst option), all that happens then is that it doesn't compute F or NF but doesn't complain about it. So something else is going on. Also, using noiseoff_inst/noiseon_inst shows up in the log file, so it must be something else... I found some very old issues related to this (long fixed) and these were bugs (it was only a couple of reports from many years ago though). Andrew.
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Forum Post: unbound variable - device property issue
Hi, I set a variable "L350" to NMOS transistor length and sweep the variable. It works well. However, after I try parameterization on its length, accidently cds shows the unbound variable issue of "L350", CIW report: CDF parameter function has problem. And when I open property of NMOS transistor by "Q", all CDF info disappear. I can forcely open property assistant view, and find many yellow exclamation mark as below. Btw, the netlisting and simulation still work with this issue. Is there anyway to recover the CDF settings as before? Thanks!
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Forum Post: CMRR simulation setup
Hello, This question has been asked multiple times and answered here: https://community.cadence.com/cadence_technology_forums/f/rf-design/27951/plotting-cmrr-and-psrr-in-cadence-virtuoso and here: https://community.cadence.com/cadence_technology_forums/f/rf-design/27951/plotting-cmrr-and-psrr-in-cadence-virtuoso/1329716#1329716 I set up my simulation test for CMRR as follows: I used the xf analysis and the result doesn't seem right. Here is what I get: I even took the reciprocal of the above response and it is not coming right. I also followed this popular method and it didn't work. What am I doing wrong? Thank you so much in advance.
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Forum Post: RE: CMRR simulation setup
Dear wgtkan, A few items came to mind when I read your post and saw your comments on your simulation result. Shawn What is it specifically about the CMRR response that "doesn't seem right"? What is the DC value of your voltage Vcm and does it keep your DC operating point of the op-amp in its high gain region of operation? Your circuit does not appear to have a load impedance. The load impedance can impact the frequency response of the amplifier and its stability. As a result, the CMMR you are observing may not be an accurate estimate of the CMRR when used in your application.
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Forum Post: RE: CMRR simulation setup
Hello Shawn, 1. The last plot seems correct but the earlier one was not right. 2. The DC value of the voltage VCm is 0.9, yes it keeps the operating point of the Op Amp in a saturation region. 3. I did not place a load impedance. I will connect a load impedance and rerun the simulation. I wanted to run the CMRR simulation using XF analysis as Andrew mentioned but It didn't work for me. Thank you for your response.
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