This video should help https://www.youtube.com/watch?v=wiSBcH3M0xM&t=12s
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Forum Post: RE: Rotating elements in the shape of a circle
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Forum Post: Allegro unrouted net for adjacent pins change to simple straight connections
Hello In Allegro 17.2, when the unrouted nets are on adjacent pins, the connection exits the IC from one pin and goes back to the adjacent pin in a complicated pattern. Is it possible to have a straight connection instead? Frank
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Forum Post: RE: Allegro unrouted net for adjacent pins change to simple straight connections
this was answered a few years ago under a slightly different question: Open the .BRD Then: Setup|Design Under "Command Parameters" Display There is an option: Ratsnest Geometry - Jogged/Straight
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Forum Post: RE: Allegro unrouted net for adjacent pins change to simple straight connections
Thanks. It works!!! I did search here. The keywords did not bring me to that previous post.
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Forum Post: Unable to save the changes made in Display Resource Editor into a file due to the "drmSuppressSaveDialogBox" variable
I'm trying to make some minor changes to my default display resource data and save it into a .drf file using File -> Save in Display Resource Editor. However, I'm getting the following message in CIW: "Display Information is modified in the current session. However Save Display Information Dialog Box has been suppressed as environment variable "drmSuppressSaveDialogBox" is set. The modified Display Information will not be saved." I tried "envSetVal("layout" "drmSuppressSaveDialogBox" 'boolean nil)", but that doesn't seem to be doing anything since the default value is already nil. Any idea what I'm missing? I'm using version ICADVM18.1. Thanks, Fari
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Forum Post: Can't add DC parameter via the annotation
Hello, This question has been asked multiple times as shown here: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41046/unwanted-empty-line-in-annotation-setup https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/42253/can-t-edit-value-of-cdf-parameters-in-edit-object-property-form https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/42253/can-t-edit-value-of-cdf-parameters-in-edit-object-property-form I followed the instruction by going to CIW > Tools > CDF > Edit and did the following: 1. Scope selected cell 2. CDF Layer selected Base 3. Library Name the desired library is chosen 4. Cell Name the preferred Cell name is selected 5. I am confused on callback setup 6. From the tab, I chose Interpreted Labels 7. Use CDS parm to display selected operating point results and added region I am attaching two pictures. The first one is what I get on the annotation balloon and the second picture is what I did to select the region dc parameter. But for some reason, region is not showing on the transistors. I consulted the PDK documentation, and I couldn't find anything. Thank you so much for your help.
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Forum Post: RE: CMRR simulation setup
Hello Shawn, My interpretation of your last plot is that it represents the differential gain of your op-amp versus frequency while the former curve represents the CMRR versus frequency. Am I correct? No. It is representing the CMRR response against frequency. I understand your concern and I saw literature of the recommended means of simulating an opamp's CMRR and followed their method. I am attaching one such useful paper here. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1375058 In some popular textbooks also the load is not added. I have done a stability analysis to determine the open-loop magnitude and phase response and checked my result by performing other open-loop gain simulation by adding high-impedance feedback components. Thank you always, Shawn.
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Forum Post: Show measurement window does not open
Hi, When I try to use the show measurement tool in APD+ free physical viewer in Win10, the show measurement window does not open. I am able to get the show element window to open but no luck with the show measurement window. I tried deleting the .geo file in my pcbenv directory but no luck. Any suggestions?? FYI..I just did a fresh install of Allegro IC Packaging 2020 APD+ Free Physical Viewer 17.4-2019 S008 [7/14/2020] Windows SPB 64-bit Edition Andy
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Forum Post: RE: what is major difference between "Symphony Team Design" option and "PCB Team Design" on Allegro PCB Designer?
thank you steve! then symphony team design is only focus on the "live" right?
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Forum Post: RE: CMRR simulation setup
Dear wgtkan, [quote userid="289980" url="~/cadence_technology_forums/f/custom-ic-design/46633/cmrr-simulation-setup/1369051"]No. It is representing the CMRR response against frequency. [/quote] Thank you for the clarification. I was confused. [quote userid="289980" url="~/cadence_technology_forums/f/custom-ic-design/46633/cmrr-simulation-setup/1369051"]I understand your concern and I saw literature of the recommended means of simulating an opamp's CMRR and followed their method. I am attaching one such useful paper here[/quote] Thank you, wgtkan, for the reference! I took a look at it using my IEEE account (without an account, one cannot view the paper). I did notice that all of the three amplifier configurations the authors propose for measuring CMRR do include the feedback network (albeit different feedback configurations). [quote userid="289980" url="~/cadence_technology_forums/f/custom-ic-design/46633/cmrr-simulation-setup/1369051"]and followed their method.[/quote] Great! Hence, I think you are on the right track to providing a good estimate of the CMRR. [quote userid="289980" url="~/cadence_technology_forums/f/custom-ic-design/46633/cmrr-simulation-setup/1369051"]I have done a stability analysis to determine the open-loop magnitude and phase response and checked my result by performing other open-loop gain simulation by adding high-impedance feedback components. [/quote] I hope the two sets of results provided some assurance of your simulation methodologies for stability. Excellent! Thank you, very much, for letting us know your results and conclusions wgtkan! Shawn
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Forum Post: How to zoom fit screen by axl command
Hi anyone. I tried to display the screen of allegro tools as center. We just only use "axlWindowFit()" but the result display fit and left side of screen. Please help me to dispay like as Zoom Fit command by axl command using. Thanks, DDR
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Forum Post: LVS not able to read layout with hierarchy.
Hi anyone know what happen why lvs result show it missing basic cell like P_18_ICS_MM . please advice. 1. (without schematic hierarchy) We create new layout for SL_PARINV. As yau can see below. LVS result for SL_PARINV it self is clean. 2. (with schematic hierarchy) We create new SL_PARINV with hierarchy schematic.and the lvs result show it missing basic cell like N_18_CIS_MM. from my point of view its like the lvs not able to read connection from layout that have hierarchy. please advice. regards Faisal.
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Forum Post: How to solve the via shorting issue?
One of the via showing an unintended connection to GND plane. Please see the following picture. My intention is to disconnect this via from GND plane and connect it to VDD_CORE plane. I have tried to delete and create a new via, still via is connecting to GND. How to fix this issue? PCB Designer version - 17.2 EDIT I understand that " Assign net to via" is an option to change the via net property. When I try for that option, it is not available for me.!!
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Forum Post: what's the Ocean command to make VIVA fitting all Y to visible X?
hello experts, in VIVA there's button we can click to fit all Y to visible X. but I'm doing Ocean script to capture the waveform so I'd like to know the equivalent Ocean command to do that.................................................................................... thanks a lot, David
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Forum Post: Floating Vpulse Influence Simulation Result
Hello I get confused recently. I am simulating a DCR (Direct conversion receiver) to get the output DC term caused by second order non-linearity of it. And I find a weird phenomenon, that is the vpulse can influence the simulaition result even if it only connects to ground. I change the frequency of it, and the simulation results changed. Is it a BUG? or something impossible? Did anybody meet situation like this? thanks
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Forum Post: OrCAD/Allegro 17.4 (SPB174) HF009-Set up or Configure Allegro EDM Servers
Hello, Recently we are working on installing OrCAD/Allegro 17.4 (SPB174) HF009 (before we used 17.2 HF63), just installed software, plan to set up EDM server in a new HW, we tried what we did when in 17.2 like this: F:\Cadence\SPB_17.4\conf>conf "Base Directory set to F:\Cadence\SPB_17.4" Aug 23 2020 09:48:18,592 INFO com.cadence.adw.conf.Conf [] - Server Setup is moved to Element, not picking any server settings here In pop up window, only two menus "Set up or Manage Company & Site" and "Set up Client", not see that "Set up or Configure Allegro EDM Servers" which we use to set up or configure a EDM server. Not quite understand what does it mean " Server Setup is moved to Element " and how we can set up EDM server in 17.4 Does anyone has the knowledge/experience? and any documentation for these configuration for 17.4? Thanks in advance! Xiaojun
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Forum Post: RE: How to solve the via shorting issue?
When you start the add connect process check the Find Filter to see what entities are set for selection. I would bet that you have "Shapes" selected, if so deselect that button and verify that you have "Clines" button selected. Once that is done use the cursor to select the end point of the escape trace to add the via. I would also look into adding to your loaded SKILL programs the change via by netname script. I hope this helps.
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Forum Post: RE: Show measurement window does not open
did you use dual monitors previously? locate your pcbenv folder and delete the allegro.geo file to see if the gui comes back.
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Forum Post: Simulating the LC tank to determine the oscillation frequency
Hello, I am trying to determine the center frequency of an LC tank for an NMOS LC VCO. I followed this note from a previous question. https://community.cadence.com/cadence_technology_forums/f/rf-design/32224/lc-parallel-circuit-at-resonant-frequency I did run an s-parameter simulation of the impedance against the frequency on the ideal LC tank and s11 produces the expected response. I am attaching the circuit and the response. On the other hand, when I use real devices, it is producing something different. I consulted the model file for the 130nm hp process but I am not getting it to produce the desired response. I am attaching the schematic and the waveform I am getting. What am I doing wrong? Thank you so much in advance.
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Forum Post: RE: How to solve the via shorting issue?
you need to make sure to select the via. then if the menu does not show up, you can type via assign net in the command line.
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