Thanks, I can confirm this behavior from my side.
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Forum Post: RE: Bind Key for Changing Multiple Layout Grid Controls
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Forum Post: EM simulation for a large CMOS system
Hi everyone, I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS). In ADS , I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane. Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have: Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue? Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance? Any insights would be greatly appreciated. Thank you in advance for your help!
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Forum Post: EMX - multiple edge pin on a same edge
Hi everyone, I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Say I have an amplifier and a 1-to-2 power divider that works up to 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the whole layout (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. So I divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance? Any insights would be greatly appreciated. Thank you in advance for your help!
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Forum Post: Orcad X PCB Editor vs Presto
I am trying to understand the thought process behind dividing up features that force one to use both editors. For e.g., one cannot align vias in Orcad X Professional Editor (only the Allegro license can), but you can align vias in Orcad X Presto. I would like to understand the logic behind forcing the use of two PCB editors with the Orcad X Pro license. I thought Orcad X Pro was the superset. Trying to transition from Xpedition, it is these little things that make it irritating. I'm using 24.1.
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Forum Post: RE: How to Set Checks/Asserts as Default View After Simulation in Virtuoso Assembler
Can, This appears to be a bug. I can reproduce it in the latest IC23.1 ISR (ISR10). Please contact customer support (submit a support case after logging in) so that this can be rectified. Andrew
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Forum Post: Recommended delimiter in DSPF for deep probing
Virtuoso IC Studio IC23.1-64b.ISR8.40 I'm having issues probing signals from an extracted view and the guides in the support.cadence.com are wrong as well.From the results browser I probe the voltage of interest and get this expression: v("u_lfxo.u_gp_lfxo_top\\/u_agc\\/in_cmp_p" ?result "tran") So one would think that using u_lfxo.u_gp_lfxo_top\\/u_agc\\/in_cmp_p as signal path in the deep probe does the job. However, nothing gets probed. I found this in the forum: deepprobe not working for extracted cellview in ADE-XL run. But the suggested underscore would also be a problem because we use underscores in the instance names. What other character could be used as delimiter that does not require escaping in the deep probe syntax? Honestly this is a task that should be very straightforward to but the tool behavior is buggy.
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Forum Post: load via options into cadence session
What is the variable to define via selection/type for vias I want to be able to load via cut type in the via option when I use the leHiCreateVia() function I want to select/load to the Via Option menu on which via I want to use Cadence version IC23.1.64b.ISR7.27 Paul
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Forum Post: How to convert my system capture project to OrCAD Capture / Allegro Design entry CIS
Hai Community, I have a project which is designed in the Allegro System capture but now want to continue that project into the OrCAD Capture / Allegro Design Entry CIS. How can I Convert my system capture project to the OrCAD Capture / Allegro Design Entry CIS. Can anyone share me the procedure / steps to perform for the conversion. Regards, Rohit Rohan
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Forum Post: RE: load via options into cadence session
Hi Paul, Please refer to this Article... How can I set default choice on Create Via form Rob,
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Forum Post: RE: Seeking Help with Non-Overlapping Placement Logic for Groups in Layout Design
Hey Hussain Aalim , I do not have a code for this but what what I can think is get the bbox for the groups and put an if statement to check whether they are same or not. If they are same at some point, move the group to a new location. Let me know if this make sense or you need to explore any SKILL APIs for this.
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Forum Post: RE: Orcad X Presto 23.1 : Save default settings of the interface
As tested in Orcad X Presto, the grid settings, color settings are getting reset to default ones, eventhough the board file has been saved with the user settings. RnD has been notified about the same and a CCR has been in Place for the issue.
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Forum Post: RE: Orcad X PCB Editor vs Presto
Regarding the specific example you mentioned, via alignment is a feature that is indeed available in Allegro, but not in the Orcad X Professional Editor. The reason for this is that Allegro has a more advanced set of features for PCB layout and editing, including via alignment, which is commonly used in high-density PCB designs. Allegro's via alignment feature allows for more complex via placement and alignment rules, which are not available in the Orcad X Professional Editor. The Orcad X Professional Editor is a PCB layout and editing tool that provides a set of features for designing and editing PCBs. However, it is not a direct replacement for Allegro, which has its own strengths and features.
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Forum Post: Correct "output variables" in "outputfile options" in "simulation settings"
My first question, complete newbee...from Germany. :--)) I simulated a gain clone amp with symmetric outputs with four LM1875 and I want to see the distortion of the symmetric amp. Please, what is the correct expression to fill in in the field "output variables" in the "output file options" window in "simulation settings"? Unfortunately I have no luck adding a picture "an error occurred...." Thank you, Gerd
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Forum Post: Can't request Tensilica SDK - Error 500
Hi, I'm looking to download Tensilica SDK for evaluation, but I can't get past the registration form:
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Forum Post: IR Drop Criteria
IR criteria: Static IR (STD) ~2% Static IR (MEM) ~1% Dynamic IR (STD) ~10% Dynamic IR (MEM) ~5% Anyone knows the reason behind this criteria? >.<
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Forum Post: Back annotate from PADS SWP file
Why does 22.1 no longer back annotate using SWP files generated from PADS? I have to open the design in 17.2 and perform the back annotation.
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Forum Post: Noise summary data per sub-block in Maestro output expressions
Hi, I have a question about printing noise summary via maestro output expressions. H ow can I print noise data using output expressions, for multiple levels of the hierarchy? I have found this article which describe the procedure using ocnGenNoiseSummary() function : https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000007MViHEAW&pageName=ArticleContent I see also Andrew Beckett referring to the above mentioned article as a solution to a similar question: community.cadence.com/.../noise-summary-per-instance However, this seems to work only if I'm to extract noise data from a single level of hierarchy. If I have the output expression "ocnGenNoiseSummary(2 ?result 'hbnoise)", it will generate a "noisesummary" directory under results directory for a hierarchy level of 2. If I am to extract data from various hierarchy levels, I should be able to generate multiple noise summary directories, such as noisesummary1, noisesummary2 where they correspond to "ocnGenNoiseSummary(1 ?result 'hbnoise)" & "ocnGenNoiseSummary(2 ?result 'hbnoise)", respectively. However this does not seem to be possible. Can you please advice? Thanks. My Cadence version: IC23.1-64b.ISR7.27 BR, Denizhan Karaca
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Forum Post: RE: Recommended delimiter in DSPF for deep probing
It seems that using $ as dspf divider works without having to escape it.
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Forum Post: RE: Recommended delimiter in DSPF for deep probing
There seems to be a hiccup in the tool though. Trying to fix this issue I used the hier_delimiter="/" option in the miscellaneous tab of the simulator->options->analog. Now, even when I delete, reset to defaults or explicitly defined to "." the delimiter doesn't return to "." I have even close the session and changed machines (I'm running in a server farm). Is there a way to set the hier_delimiter as an environment variable?
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Forum Post: EM simulation for a large CMOS system
Hi everyone, I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS). In ADS , I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane. Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have: Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue? Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance? Any insights would be greatly appreciated. Thank you in advance for your help!
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