Hi AAronSymko, Thank you very much foryour solution and time. Please see my response to Andrews solution as well. With kind regards, Sjoerd
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Forum Post: RE: How to flatten a disembodied property list (DPL)?
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Forum Post: Deleting ORcade X from previous device
I recently downloaded OrCAD X on a Windows device but encountered issues running it on my MacBook. To address this, I attempted to install it on Parallels Desktop on my Mac. However, I was unable to proceed because I have exceeded the allowed installation attempts. I would like to uninstall OrCAD from the previous device and transfer the license to my Mac. Could you please guide me on how to properly deactivate or uninstall OrCAD on the old device?
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Forum Post: RE: How to flatten a disembodied property list (DPL)?
Sjoerd, The trouble is that DPLs are not really intended to be treated as an ordered data structure. The mechanism is that when you add a new slot via dpl->slot=value then if there's no key called "slot" in the DPL already, it will insert it at the beginning (after the initial dummy value in the DPL) because that's the most efficient place to add it. The ->? operator happens to collect the slot names in reverse, but I don't think that's documented behaviour (I would be wary of assuming that). Because you are constructing the top-level slots in sequence, these are reversed - but the lower level DPLs are specified literally as lists and so they are in the order they were specified. You'd need to know the expected order in each level which adds to the complexity. This variant might do what you want: CCFflattenStrangeDPL(interfaceVars->layout->order t) ; t is to reverse the top level procedure(CCFflattenStrangeDPL(dpl @optional reverse) let((key value result subResult) dpl=cdr(dpl) while(dpl key=car(dpl) value=cadr(dpl) dpl=cddr(dpl) subResult= copy( if(listp(value) && !car(value) then ; don't pass down the reverse flag ; so only reverse the top level CCFflattenStrangeDPL(value) else value ) ) if(reverse then result=cons(subResult result) else result=lconc(result subResult) ) ) if(reverse then foreach(mapcan item result item) else car(result) ) ) ) Andrew
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Forum Post: RE: Characterizing cells with verilog-A models by liberate, but the model or instance can not be found
As I said, -extsim_model option is needed for leaf cells with verilogA model. My diode example is just an example that can be applied to other devices. for your nmos, define_leafcell -extsim_model -type nmos -pin_position {0 1 2 3} {nch} Also, try with/without the verilogA mode in your extsim_model_include and read_spice. You probably should not include it, as it has been defined in extsim_deck_header. You have not clarified whether you have user-defined define_arc command. Liberate may not be capable of automatically generate arcs/vectors with designs that are not CMOS based. The sitution is not clear, if your design has only devices with verilogA model. If the above settings do not work, please contact customer support with a full test case. Guangjun
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Forum Post: RE: Unable to run PVS Quantus extraction in cds_ff_mpt (finfet 18nm)
Hi Andrew ----------------------------------------------------------------- Name : quantus - Quantus - (64-bit) Description : Quantus Extraction program Version : 20.1.0-p052 Build Ref. No. : 052 IR Build No. : 052 Build Date : Fri Nov 29 10:55:59 PST 2019 ----------------------------------------------------------------- sub-version ICADVM18.1-64b.500.13 PVS version PVS 20.11-s024-64b
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Forum Post: RE: How to flatten a disembodied property list (DPL)?
Hi Andrew, Thank you for the explanation. Your explanation confirms what I see happening. I'll test the code later today. By the way: is there an other (prefered, easily "traversable" ) way of specifying order in Virtuoso/SKILL? With kind regards, Sjoerd
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Forum Post: RE: Indago training
Yes. There is a support article on how to run a basic example with Verisium Debug (the new name for "Indago") here . There is a RAK (Rapid Adoption Kit) for post process debugging here . The user guide is available here . If you have additional questions about Verisium Debug, feel free to contact your Cadence support AE or file a support ticket. Thanks. - Doug
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Forum Post: RE: Characterizing cells with verilog-A models by liberate, but the model or instance can not be found
I'm sorry I overlooked -extsim_model option before, I have added this option as suggested，and also define arcs in template.tcl. as follow; " try with/without the verilogA mode in your extsim_model_include and read_spice " (According to my understanding, just remove these two lines #set_var extsim_model_include $rundir/MODELS/section_mos.scs #set spicefiles $rundir/MODELS/section_mos.scs but what about read_spice? I don't understand， “read_spice $spicefiles” seems can not be removed. ),, it shows the same error as before. the log and template file as follows template.tcl: if {[ALAPI_active_cell "INVD1"]} { define_cell \ -input { I } \ -output { ZN } \ -pinlist { I ZN} \ -delay delay_template_5x5 \ -power power_template_5x5 \ INVD1 define_leakage -when "(I * !ZN)" INVD1 define_leakage -when "(!I * ZN)" INVD1 # delay arcs from I => ZN negative_unate combinational define_arc \ -vector {FR} \ -related_pin I \ -pin ZN \ INVD1 # delay arcs from I => ZN negative_unate combinational define_arc \ -vector {RF} \ -related_pin I \ -pin ZN \ INVD1 log: LIBERATE parameter "slew_lower_rise" set to "0.3" LIBERATE parameter "slew_upper_rise" set to "0.7" LIBERATE parameter "slew_lower_fall" set to "0.3" LIBERATE parameter "slew_upper_fall" set to "0.7" LIBERATE parameter "measure_slew_lower_rise" set to "0.3" LIBERATE parameter "measure_slew_upper_rise" set to "0.7" LIBERATE parameter "measure_slew_lower_fall" set to "0.3" LIBERATE parameter "measure_slew_upper_fall" set to "0.7" LIBERATE parameter "max_transition" set to "1.5e-09" LIBERATE parameter "extsim_deck_header" set to " .hdl /homes/RuiLi/liberate/file/liberate/MODELS/veriloga.va" INFO (LIB-511): (define_leafcell): Leafcell 'nch' (instance) has been identified with pin_position (0 1 2 3) mapped to (D G S B). LIBERATE parameter "extsim_exclusive" set to "1" LIBERATE parameter "spectre_pwr" set to "0" LIBERATE parameter "simulator" set to "ski" LIBERATE parameter "char_library_skip_var_list" set to "" Start Characterizing Library at (Fri Jan 17 22:45:26 CST 2025) *Info* Removing all types *Info* Max Shared Memory Segments : 4096 *Info* No unattached Shared Memory Segments belonging to RuiLi out of 441 total. *Info* Max Semaphore Arrays : 128 *Info* No unattached Semaphore Arrays belonging to RuiLi out of 1 total. *Info* Max Message Queues : 32000 *Info* No Message Queues *Info* Zombie Process 'lsb_release' isn't 'spectre' related. Skipping. *Info* Zombie Process 'whoami' isn't 'spectre' related. Skipping. *Info* Zombie Process 'lsb_release' isn't 'spectre' related. Skipping. *Info* Zombie Process 'whoami' isn't 'spectre' related. Skipping. WARNING (LIB-103): When using Spectre-SKI, runtime may significantly improve when using an extsim_model_include/define_leafcell flow. This is needed to enable the Spectre modellib flow. WARNING (LIB-909): (read_spice): Could not find a model/subckt definition for instance 'XM0' named 'MoS2FET' with '3' terminals. Liberate will attempt to guess the device type. Read the models in read_spice or use define_leafcell to map the name to a model/subckt and rerun. WARNING (LIB-933): To enable automatic leaf-cell recognition, the variable 'extsim_model_include' is required. WARNING (LIB-1007): (char_library): This LIBERATE release was qualified with MMSIM version '18.1.0.235.isr3' but older version '15.1.0.284.isr1' was detected. Older versions of MMSIM are not recommended. Update to the qualified MMSIM version and re-run. INFO (LIB-956): (read_spice): Reading file: '/homes/RuiLi/liberate/file/liberate/NETLIST/INVD1.sp'. INFO (LIB-940): The parser has identified the following leaf cells. Review these for missing or incorrect settings and if needed, add them to your Tcl script and rerun. INFO (LIB-906): (AUTO): define_leafcell -type black_box -pin_position {0 1 2 3} INVD1 INFO (LIB-907): (AUTO): define_leafcell -element -type black_box -pin_position {0 1 2} MoS2FET INFO (LIB-943): Finished reading netlist(s) at Jan 17 22:45:27. INFO (LIB-711): Feature 'Spectre_char_opt' exists in the license pool. The parameter 'spectre_use_char_opt_license' will be set to '1'. *Info* (char_library) : SKI process child signal handler enabled. INFO (LIB-966): Using Spectre version 15.1.0.284.isr1 located at: /opt/cadence/MMSIM151/bin/spectre. *Info* Use temporary directory '/homes/RuiLi/liberate/file/liberate'. LIBERATE parameter "extsim_deck_dir" defaulted to sanjose:/homes/RuiLi/liberate/file/liberate/decks.sanjose.T20250117224524081610S0063769 *Info* : Initializing SKI environment... Initializing Spice *Info* No global model has been read in. Will expect model defined inside instance. Building library database ERROR (LIB-203): (char_library): Cell 'INVD1' is scheduled for characterization but has no netlist, has an empty subckt or has no port on the subckt. This cell will be skipped. Check the netlist and rerun. WARNING (LIB-961): (char_library): Leakage deck initialization was requested using '.ic', but the 'leakage_sim_duration' was set to '0'. This may lead to unexpected leakage characterization results. Change 'leakage_sim_duration' to a positive non-zero value in seconds or change the setting of 'set_sim_init_condition' and rerun. MEM=2475 MB MEM=2475 MB MEM=2475 MB *Info* (char_library) : SKI process child signal handler disabled. MEM=2508 MB Performance statistics (96 thread(s)): Spectre cpu time = 0.00 hours (0.00 seconds) Total PreProcessing time = 0.00 hours (0.00 seconds) Total cpu time = 0.00 hours (0.00 seconds) Wall clock time = 0.00 hours (1.00 seconds) Characterization finished at Fri Jan 17 22:45:29 2025 Characterization statistics: Number of cells to characterize = 1 Number of define_cell commands = 1 Number of passing cells = 0 Number of failing cells = 0 List of failing cells {} Number of skipped cells = 1 List of skipped cells {INVD1} Finished Liberate Execution. Updating library database /homes/RuiLi/liberate/file/liberate/LDB/example.ldb.12.gz Memory usage: 2483 Mbytes LIBERATE parameter "mx_format_expand_buses" set to "0" LIBERATE parameter "ecsm_multi_stage_cap_mode" set to "0" LIBERATE parameter "ccsp_mode" set to "0" LIBERATE parameter "ecsm_waveform_error_adjust" set to "0x2" WARNING (LIB-989): (write_library): This command will be skipped because there is no cell data to write. Characterize or read the cell data and rerun. WARNING (LIB-989): (write_library): This command will be skipped because there is no cell data to write. Characterize or read the cell data and rerun. Writing datasheet in text format to /homes/RuiLi/liberate/file/liberate/DATASHEET/example.txt *Error* (write_datasheet) : No cell groups found in the library /homes/RuiLi/liberate/file/liberate/DATASHEET/example Peak memory usage: 2.45 GB Peak virtual memory usage: 1.45 GB Peak physical memory usage: 0.99 GB Wall time : 0.00 hours (5.00 seconds) LIBERATE exited on sanjose at Fri Jan 17 22:45:29 2025
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Forum Post: RE: Characterizing cells with verilog-A models by liberate, but the model or instance can not be found
I wonder if something else should I add to char.tcl to load a external verilogA model to liberate. it seems model cannot be recognized. I think this discuss is Similar to my situation，but the error is different.It's a pity Characterizing library for emerging 2DFETs with in-house .va based models
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Forum Post: RE: Characterizing cells with verilog-A models by liberate, but the model or instance can not be found
The documentation on extsim_model_include, read_spice adn define_leafcell is quite clear. given your first script, try the following changes, 1. add x to all your M/D/R/C/N/P* instances of MOS/Diode/Res/Cap/BJTs 2. define_leacell for nmod, define_leafcell -extsim_model -type nmos -pin_position {0 1 2 3} {nch}. make sure the pin order in your model file is DGSB. The latest logfile indicates you have another device, MoS2FET. Does this device have a spice model that is included in file 'section_mos.scs'? If it is a 3-terminal MOSFET, eg. B-S shorted, then try -pin_position {0 1 2 2}. 3. keep your set_var extsim_deck_header ".hdl /support/diode.va" 4. remove va model from 'section_mos.scs', if it is included. Then keep extsim_model_include and read_spice . 5. you need -user_arcs_only for char_library command 6. you may need '-extsim spectre' in char_library command. try this only if all above still do not work If the characterization still does not run, please raise a Case with Cadence customer support. It will also save you time to fully explain your case. Regards, Guangjun
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Forum Post: RE: In Win11 24H2 OS, Allegro X Capture23.1 HF006 has issues with zooming in and out
I recently updated to Windows 11 and I have the same problem. The trick of turning off the grid reference helps reducing the scale of the problem, but it is still there. I raised a ticket at my support tech. And fortunately, Cadence has submitted a CCR 3100527 on the issue. Hopefully, it will be fixed, soon... If more people raise the issue to their support tech, it will motivate Cadence to work harder on a solution.
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Forum Post: Modify mechanical symbol dimensions
Hello, I have a question regarding mechanical symbols. For a course that I am currently enrolled in at my university, our professor gave us a project with multiple requirements. He specified that we should use MTG125 for the mounting holes, but we have a requirement stating that the hole diameter should be 3.2 mm (126 mils instead of 125 - the default value for MTG125). I have tried to modify the symbol itself (after making a copy of the original one) and adjusted its pad (modified all the dimensions accordingly). However, it's not working - the symbol remains the same as MTG125. While I understand there's a very small difference between 125 and 126 mils - and this is just a university project - I still need to implement this requirement. Does anybody know how I can modify it? The professor showed us how to do this in OrCAD 17.2 PCB Editor (Tools->Padstack->Modify Design Padstack, which then opens in Padstack Editor), but I am using OrCAD X Presto. How can I solve this problem?
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Forum Post: back annotating bussed terminal DC voltages with cdsterm in Symbol
Unfortunately, Cadence Forum had put this LOCK feature in the forum, so we cannot "necro post" to a question, even if we found the solution to a question thanks to the reply in the topic. I want to replying to this post : Annotating bussed terminal voltages with cdsTerm() I found a solution to put instead of the cdsTerm("myBUS ") in the symbol label Here is my answer : strcat("0b" apply('strcat foreach(mapcar cds list(cdsTerm("ADJUST ") cdsTerm("ADJUST ") cdsTerm("ADJUST ") cdsTerm("ADJUST ") cdsTerm("ADJUST ") cdsTerm("ADJUST ") cdsTerm("ADJUST ") cdsTerm("ADJUST ")) sprintf(nil "%d" floor(evalstring(cds)))))) Unfortunatly, we cannot loop on index with only one name to modify, since cdsTerm will not evaluate sprintf. (mayby there is a trick with apply/eval/evalstring, but i did not try. cdsTerm(sprintf(nil "qin7 " 0)) ;=> error Hope it helps. ++
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Forum Post: RE: Vmanager change error attributes for all future regressions
Fixed, I just used the "-xmwarn RNFNSH" argument in xrun.
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Forum Post: RE: The code statements that not in procedure can not be saved to context file when build context file
hi Andrew, is my reply description not clear enough? Yush
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Forum Post: RE: back annotating bussed terminal DC voltages with cdsterm in Symbol
evalstring( sprintf(nil "cdsTerm(%L)" bitname) ) should work, and than loop over dbProduceMemName( "ADJUST " ), might be more readable. Regards,
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Forum Post: RE: Modify mechanical symbol dimensions
Try this: Set the Properties to Pins only, select the placed MTG125 in the canvas with a left-click. In the General group you will see the Padstack, PAD125, as a link, left-click that to get the Search to show the placed MTG125 symbols in the BRD. Move to the search results, the Padstack column will list the PAD125s, right-click in one of the PAD125 cells and take Replace Padstack, then you can Update All, or Update Selected and use the "..." to browse for the replacement Padstack, and then Apply. (You may need the Ignore Locked set if the MTG125 Symbols are locked)
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Forum Post: RE: The code statements that not in procedure can not be saved to context file when build context file
Yush, It's clear. I just haven't had a chance to do the relevant experiments and give you a solution (I've had the day job taking up my time). I hope to get to this soon. Andrew
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Forum Post: Stabindex and S1/S2 in Sprobe Cadence
Hi, I added Sprobe to the LNA I designed to check the stability of interstages. But the results generated by Sprobe confuse me. For StabIndex, it is always less than 1. However, at some frequency, S1 and S2 will be greater than 1, and Z1 and Z2 will also have negative real impedance at that moment. I am wondering whether the circuit is in the unconditional stable state or unstable in this case? Thanks!
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Forum Post: RE: *Error* blankstrp: argument #1 should be a string (type template = "t") - nil
From this stack trace, this appears to be a bug with the Calibre interface from Siemens EDA. You should contact their customer support. It is certainly failing in their code (the "mgc" prefix is from "Mentor Graphics Corporation" (the previous name of the company). Andrew
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