Hi JuanCR Thank for responding. This is the shown directory. DirWork | |__*.brd | |__test.il | |__*.dll | |__app.exe i've run skill system("app.exe")-> it work me. I believe it's okay. After loading the skill in the window command line, I did not encounter any errors. However, I detected that the process 'app.exe' is running on my computer. Besides, link Skill and GUI python. it seems work well. Finally, I would like to note that I am currently using the Allegro PCB editor and unfortunately. Best reguards, HoangKhoi.
↧
Forum Post: RE: how to link Skill and GUI c++ (Qt5)
↧
Forum Post: Display pads coordinates
Hey community! I would like to display coordinates (and maybe some more useful information) about the padstacks used in the footprint (.dra file). I have managed to prepare the script that shows that information in the command window, but I would prefer to have it displayed in some more user friendly way (for example below the padstack, with the ability to toggle the visibility using some shortcut). Is there any way to achieve such thing? I would be very grateful for some similar examples, as I have no experience with making custom UI in Cadence.
↧
↧
Forum Post: sampled PAC transfer function to discrete step response
I am simulating an amplifier followed by 4 track and hold circuits, each sampling consecutively (interleaved). The duty cycle of each of the four clocks is about 20% i am running sampled PAC, and i am choosing the sampling time of one of the four clocks, and i am looking at the output of each of the 4 TH, to see the effective BW of the amplifier+TH. There were a couple of things that i cannot explain to myself 1) It seems that I have some ringing on the TF at the sampling frequency. Is this a memory affect of the TH? i see that the size of the ringing depends on the clock duty cycle 2) I expect the TH that i am using as the trigger clock to have a different response than the other 3 (clock injection makes them have different LF gain) but i expect the other 3 to have roughly the same response, but i see that the phase of the ringing is different between each of the other 3 3) Because of the ringing, i want to convert the TF to a step response with a inverse fft. since there is no built in function, i think i can take the conjugate, than put it through a regular fft, then take the conjugate again. the problem is that the fft is failing when i put in complex frequency data
↧
Forum Post: RE: Display Your Know How: Thermal Relief
You could change the narrow trace to a bigger shape and change both to full contact. This way both sides would have similar thermal properties and the risk of tombstoning would be reduced. Bonus note: If the component is a DFN type, the risk of tombstoning is not so big, because of reduced leverage on the terminals. Agree?
↧
Forum Post: RE: veriloga error between spectre and ams
I am planning to anyway go ahead with 1995 style for now since cadence support also mentioned that they don't support ANSI style for AMS(since it is not part of LRM) But putting the code and context below so that it might help someone later if there is a solution for this and Cadence decides to support ANSI style in AMS. module sample ( input electrical VDD, input electrical VSS, input electrical i_a, output electrical [3:0] o_b ); localparam b_val = 13; localparam b_bits = 4; integer compare_bit; genvar i; analog begin for(i=0; i >i)&1; V(o_tm_amp_corr[i]) still the error is same.
↧
↧
Forum Post: skill function problem
i want to achieve a function, when enterPath() is ruuning, i want to click right button mouse then display a menu i create, how could i do that. The second question is how to know right button mouse is click or not
↧
Forum Post: RE: Replace instances in a schematic by other instances
Hi, I open my schematic, and put this into CIW: foreach(ih geGetEditCellView()~>instHeaders when(ih~>libName=="devices_symbols_hv" && ih~>cellName=="pdomos50" dbSetInstHeaderMasterName(ih "bhvLib" “pmos_spectre" ih~>viewName) ) ) But nothing happens. So I need to press Control-C. Can you see a mistake? It would be also good to have a mapping from multiple target cells to a single final cell, e.g. we have different resistor types but I want to map to an (almost) ideal resistor. Bye Stephan
↧
Forum Post: RE: Open Design in Assembler Test can cause overwriting of the design
Hi Andrew, This is the solution to my problem: envSetVal ( "adexl.gui" "openDesignAccessMode" 'cyclic "a" ) Have it now in my .cdsinit. I am happy, thanks!
↧
Forum Post: RE: Component in Capture not visible
As it may need data sharing to debug this issue, I will be contacting you through separate channel of communication.
↧
↧
Forum Post: RE: Workspace not uploading & workspace configuration get error "unable to get local issuer certificate"
Which version of the tool you are using?, Could you upgrade to 24.1 ISR 2 and let me know if you are still facing issue.
↧
Forum Post: RE: Metric Prefix
You can't change the numbers on the ticks - if you edit the properties of the axis, you can change between suffix and engineering notation, but this is just for the multiplier shown next to the axis. If you want this, please contact customer support (submit a support case after logging in) to request an enhancement. Andrew
↧
Forum Post: Layers list for creating symbol for PCELL
I completed creating PCELL for layout, now I am trying to create a symbol for schematic instance for the pcell, I want to know what all layers are available in schematic, how can I check them?
↧
Forum Post: RE: General stability and usability of Orcad EDM
OrCAD EDM improves team collaboration but has some quirks, especially with file handling. Your concern about manual changes in both the local workspace and vault is valid, as conflicts can arise. The filesystem vault is a decent choice, though SVN, while older, is stable for version control. Basic check-in/out works well, but larger projects may reveal limitations. Overall, if Capture’s file management issues don’t cause major problems for you, EDM should be a helpful addition.
↧
↧
Forum Post: RE: Layers list for creating symbol for PCELL
The symbol uses pre-defined layers. Just create the shapes and pins using the symbol editor.
↧
Forum Post: RE: Layers list for creating symbol for PCELL
I want to know what are those pre-defined layers, because I am creating it using code, so need to add them in layers section.
↧
Forum Post: RE: Layers list for creating symbol for PCELL
If you ok using SKILL then it's probably easier for you to open an existing symbol and interogate the objects. i.e. Select the shape then css()~>??
↧
Forum Post: RE: Custom net colors not hidden in 3DX viewer
I would call this a bug... But you can remove the net colors in the 3D canvas by: Visibility window, Net tab, find the net(s), right click the color, click the "-" in presets window
↧
↧
Forum Post: RE: Layers list for creating symbol for PCELL
This is also covered in the Schematic Editor Documentation: https://support.cadence.com/apex/techpubDocViewerPage?path=comphelp/comphelpIC23.1/chap13.html#customizingschematicobjectattributes Andrew
↧
Forum Post: RE: Custom net colors not hidden in 3DX viewer
Agree. Also noticed that you can remove the net colors in the 3DX canvas. Thanks.
↧
Forum Post: RE: Component in Capture not visible
Capture only supports positive coordinates from the Top Left, Set the Page Size to as large as you can through Schematic Page Properties. Click in the Schematic Page to activate it, press Control+A to select everything. If there is a Title Block at the lower right, control+click that to deselect it, hover over one of the visible, and selected, parts in the schematic page to get the "four pointed" cursor, then click and drag to move the parts into the Page.
↧