Hello, I want to iterate through all the flat nets in my hierarchical design in OrCAD Capture using a Tcl/Tk script. For each net, I need to print the flat net name, the reference designators of the components it is connected to, and the relevant pin numbers of these components (for example: N4958340: U1.2 R11.1 U3.1 , N9487723: U1.1 U1.3 ). However, I am having trouble retrieving the reference designators of the part occurrences. I can only access the reference designators of the part instances, but that is not what I need. Below is my code so far—perhaps someone can help me: variable cstr DboTclHelper_sMakeCString variable str DboTclHelper_sGetConstCharPtr set dsn [GetActivePMDesign] set lStatus [DboState] set lNullObj NULL # Get iterator for flat nets set netIter [$dsn NewFlatNetsIter $lStatus] if {$netIter == $lNullObj} { return } # Iterate over flat nets set net [$netIter NextFlatNet $lStatus] while {$net != $lNullObj} { # Get net name set netNameCStr [$cstr] if {[catch {$net GetName $netNameCStr}]} { set netName "" } else { set netName [$str $netNameCStr] } if {$netName != ""} { # Get port (pins) connected to this net set pinIter [$net NewPortOccurrencesIter $lStatus] set pinList {} set pin [$pinIter NextPortOccurrence $lStatus] while {$pin != $lNullObj} { set pinInst [$pin GetPortInst $lStatus] # Get reference designator into $refdes # How to get it? I need to find the part occurrence somehow, either from the port occurrence or from the flat net, but how? # Get pin number set pinNumCStr [$cstr] if {[catch {$pinInst GetPinNumber $pinNumCStr}]} { set pinNum "" } else { set pinNum [$str $pinNumCStr] } if {$refdes != "" && $pinNum != ""} { lappend pinList "$refdes.$pinNum" } set pin [$pinIter NextPortOccurrence $lStatus] } delete_DboFlatNetPortOccurrencesIter $pinIter # Store the net and its pins (sorted for consistency) if {[llength $pinList] > 0} { dict set netsdict $netName [lsort $pinList] } } set net [$netIter NextFlatNet $lStatus] } delete_DboDesignFlatNetsIter $netIter
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Forum Post: Get part occurrences reference designators and pin numbers connected to a flat net
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Forum Post: Netlisting error
I'm using Virtuoso version 'ICADVM20.1-64b.500.27 I'm running a simulation , choosing 'ams' as the simulator. When I simulate after adding a certain standard cell from my PDK (GF 22FDSOI), I get the below netlisting error: "*Error* nmpIsLegalVerilogAMS: argument #1 should be a string (type template = "t") - nil ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist. *ERROR* (AMS-1245): AMS UNL netlisting has failed because of errors in the design. Right-click the test name on the Outputs assistant pane and check Output Log->Netlister Log for errors. Correct your design and netlist again. ...unsuccessful. *Error* failed at creating netlist" The netlister log has only the below info: INFO (VLOGNET-60): The stimulus name mapped table will not be printed in the "/sim/**/netlist/digital/testfixture.verilog" file. To print the stimulus name mapped table, set simVerilogPrintStimulusNameMappingTable = t either in CIW or the .simrc file before invoking Verilog netlister. INFO (VLOGNET-62): Database internal net names will be printed for floating instance ports. To prevent them from being printed, set simVerilogProcessNullPorts = t either in CIW or the .simrc file. INFO (VLOGNET-64): All cellviews in the design will be printed in the Netlist Configuration list. If you want to print only those cellviews that need to be re-netlisted in the list, set simVerilogIncrementalNetlistConfigList = t either in CIW or the .simrc file. INFO (VLOGNET-68): The initial state of stimulus of all inout pins is set to "z". To get inout pins with initial state of "0", set hnlVerilogIOInitStimulusStr = "0" either in CIW or the .simrc file. WARNING (OSSHNL-941): Failed to open the sameCellNamesInMultipleLibs file '/sim/**/netlist/digital/ihnl/sameCellNamesInMultipleLibs', in the append mode. Ensure that you have the write permission for the mentioned file. INFO (VLOGNET-118): Using connection by name (explicit connections) for all stopping and non-stopping cells. How do I debug the error ?
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Forum Post: RE: how to copy a part of design
Hi. There are a number of ways to do this. The easiest method since you also have a schematic is to save out your existing design under a new name. Remove what you do not need from your schematic and run a netlist. Update the new board with updated netlist so as to align both schematic and pcb. The result will be you have a starter board for your new project. Resize the board outline shape to the new board size you need. Best Regards.
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Forum Post: Orcad X Capture CIS (23.1) location of visible properties change if I rotate schematic symbol
Hi all, When I add a component from my database in my schematic page, the visible properties get arranged in the same way as I have them defined in my symbol. For example, when I place a capacitor, it is shown like this: If I rotate the capacitor once, the property locations change to: Now, if I rotate it in order to have the initial orientation as when I placed the component from the library, the location is fixed like shown in the picture: I can not find a way how to have the visible properties, especially the dielectric value and the voltage value be the same as when I initially place the component from the database and on to the schematic. Is there a way that I can have the visible properties reset to the location defined in the symbol's library i.e. on the same location when they initially appear when they are placed in the schematic page from my library? Many thanks!
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Forum Post: Allegro version 23.10.008 3D Canvas Preferences Color Assignments
Folks, I cannot seem to assign a color to the different layers inside the 3D mapper Preferences. See below: I am in the correct mode "Design colors", but nothing chnages when I attempt to change any layer to a color I select. Am I doing something incorrect? Chris
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Forum Post: RE: Get part occurrences reference designators and pin numbers connected to a flat net
I replied to this, but it needs to be approved, spam filter got mad at me this time
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Forum Post: RE: how to copy a part of design
not if you tick a few more options when exporting the subdrawing like shown below:
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Forum Post: RE: Orcad X Capture CIS (23.1) location of visible properties change if I rotate schematic symbol
Have a look at convert view (when defining your lib part), some say it can help although I admit I didn't use it.
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Forum Post: RE: how to copy a part of design
Actually, a schematic can be used within another schematic, as a reference (exactly like in hierarchical designs). This means that you don;t need the workaround of stripping the design and all other tricks. Thus, someone can work on a specific page/module which then can be used in the master design without much effort. This is a great feature when 2 or more people are working on the same project. Reuse modules in PCB are also part of this process. I've only seen this (in combination with the above schematic comment) once in 20 years and I don't remember other details. It might be available only in Allegro.
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Forum Post: RE: Get part occurrences reference designators and pin numbers connected to a flat net
This one's very tricky as you need to do processing of the net from hierarchy to flat. There will be a lot to iterate and check. An easier way is to generate the netlist from Capture and parse the generated netlist file with your TCL script. This one's much easier and grants: Your netlist generates without errors You don't miss anything during net processing (you might have duplicated net aliases, ports and offpage ports). A valid, reliable and simple file to process each time you want to do your tricks. What you get in the netlist is exactly what goes into PCB You can generate the netlist manually or automatically, through the TCL (replay GUI actions) Look in the ./allegro/pstxnet.dat file. The flatnet structure is quite simple. You get the net_name and then the node_name which is basically the pin NET_NAME 'ADC12_4' '@SCM-0024_A.SCM-10013(SCH_1):ADC12_4': C_SIGNAL='@\scm-0024_a\.\scm-10013\(sch_1):adc12_4'; NODE_NAME J26 4 '@SCM-0024_A.SCM-10013(SCH_1):INS16692064@ADK.TSW-106-07-G-D.NORMAL(CHIPS)': 'B2':; NODE_NAME J8 1 '@SCM-0024_A.SCM-10013(SCH_1):INS16782590@ADK.SMA CONNECTOR.NORMAL(CHIPS)': '1':; NODE_NAME R4 1 '@SCM-0024_A.SCM-10013(SCH_1):INS16782622@ADK.RES.NORMAL(CHIPS)': '1':;
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Forum Post: Exporting Layout Views as SVG Using SKILL in Allegro
Hello Community, Is there a way to convert layout views to SVG format using SKILL? For example, I'd like to export film views such as Assembly, Soldermask, etc. I’m looking for methods or best practices to generate high-quality SVG output directly from Allegro using SKILL scripts. Thanks in advance BR Samba
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Forum Post: RE: Get part occurrences reference designators and pin numbers connected to a flat net
@ VB202505089850 Please find the the code below i have added below section in your code to get placed part and then refdes.: ++++++++++++++++++++++++ set lPropRefdesStr [DboTclHelper_sMakeCString "Part Reference"] set lPropValStr [DboTclHelper_sMakeCString] set lPlacedINst [$pinInst GetOwner] set lState [$lPlacedINst GetEffectivePropStringValue $lPropRefdesStr $lPropValStr] set refdes [DboTclHelper_sGetConstCharPtr $lPropValStr] +++++++++++++++++++++++++++++++++ variable cstr DboTclHelper_sMakeCString variable str DboTclHelper_sGetConstCharPtr set lPropRefdesStr [DboTclHelper_sMakeCString "Part Reference"] set lPropValStr [DboTclHelper_sMakeCString] set dsn [GetActivePMDesign] set lStatus [DboState] set lNullObj NULL # Get iterator for flat nets set netIter [$dsn NewFlatNetsIter $lStatus] if {$netIter == $lNullObj} { return } # Iterate over flat nets set net [$netIter NextFlatNet $lStatus] while {$net != $lNullObj} { # Get net name set netNameCStr [$cstr] if {[catch {$net GetName $netNameCStr}]} { set netName "" } else { set netName [$str $netNameCStr] } if {$netName != ""} { # Get port (pins) connected to this net set pinIter [$net NewPortOccurrencesIter $lStatus] set pinList {} set pin [$pinIter NextPortOccurrence $lStatus] while {$pin != $lNullObj} { set pinInst [$pin GetPortInst $lStatus] # Get reference designator into $refdes # How to get it? I need to find the part occurrence somehow, either from the port occurrence or from the flat net, but how? set lPlacedINst [$pinInst GetOwner] set lState [$lPlacedINst GetEffectivePropStringValue $lPropRefdesStr $lPropValStr] set refdes [DboTclHelper_sGetConstCharPtr $lPropValStr] # Get pin number set pinNumCStr [$cstr] if {[catch {$pinInst GetPinNumber $pinNumCStr}]} { set pinNum "" } else { set pinNum [$str $pinNumCStr] } if {$refdes != "" && $pinNum != ""} { lappend pinList "$refdes.$pinNum" } set pin [$pinIter NextPortOccurrence $lStatus] } delete_DboFlatNetPortOccurrencesIter $pinIter # Store the net and its pins (sorted for consistency) if {[llength $pinList] > 0} { dict set netsdict $netName [lsort $pinList] } } set net [$netIter NextFlatNet $lStatus] } delete_DboDesignFlatNetsIter $netIter
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Forum Post: Allegro skills
Anyone is having output generator skill
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Forum Post: RE: Get part occurrences reference designators and pin numbers connected to a flat net
Thank you andakConsultingLtd , it is an interesting idea. I will try it.
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Forum Post: RE: Get part occurrences reference designators and pin numbers connected to a flat net
Thanks CadAP , but i think it will only give me the Ref Des of the part instances, isn't it? I need the Ref Des of the part occurrences. Since you use: set lState [$lPlacedINst GetEffectivePropStringValue $lPropRefdesStr $lPropValStr] Where lPlacedINst is the part instance.
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Forum Post: RE: Exporting Layout Views as SVG Using SKILL in Allegro
you can export them to pdf for now.
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Forum Post: creating output expression while doing parametric sweep
Hi, I am running a parametric sweep in Cadence Virtuoso and I want to create an expression that takes the difference of a voltage for the last parameter value and the first parameter value. How can I do that? I want to create expression for that so that when the simulation is done that expression is calculated and gives me the difference. But then the question is can the simulator evaluate that expression without me going to the calculator. What I mean is that when it simulated the 1st parameter value spectre would not have yet the results for the last parameter value and then what will be the result of that expression? Is it at all possible? And I would also like to do that for parametric sweep with Monte-Carlo. I would rather not go do Ocean. I think this will complicate things too much. Thanks Svilen
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Forum Post: RE: Exporting Layout Views as SVG Using SKILL in Allegro
But is there any other alternative?
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Forum Post: RE: Exporting Layout Views as SVG Using SKILL in Allegro
You can use an online tool or Inkscape to export an SVG from a PDF. Alternatively, a skill can do the job, but there is a significant amount of work since every single database element needs to be transferred to SVG.
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Forum Post: RE: Exporting Layout Views as SVG Using SKILL in Allegro
Certainly you can use Skill to convert to your layout features to SVG and I have done exactly that. It's not difficult but it does involve a large amount of code writing and a reasonable understanding of SVG syntax. My advice is to start writing functions to convert each element into SVG - lines, arcs, polygons, pads etc. Allow for location, scale, colour, transparency etc in each function. Good luck!
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