Hi There, I copied a project folder from somebody who made the project: schematics and PCB by mixing our "shared library" in the network and their local folders, such as download folder. Part Manager shows errors (exact word "Approved: Not Found") because parts that are pointing at their local directories can not be reached from my PC. Components with those error status can't not be imported to my PCB. I could copy the .OLB files from them and place them somewhere in the network. The question is how to change the pointer to other folders? Thanks.
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Forum Post: Source Library Modification
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Forum Post: RE: Issue with Level=3 MOS model in Spectre
Thanks for this information. I simulated it in Qspice. I am trying to dig what are the default W/L this would use. So this is something that is different even though we are importing a Spice model I did not know that the Spice defaults are not known by Spectre. So this is a good caution for me for the future. I am trying to see if I can get an alternate model or a Pspice model from somewhere and try that. If I create a Pspice cell view would that be equivalent to pspice_include?
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Forum Post: RE: Issue with Level=3 MOS model in Spectre
[quote userid="472875" url="~/cadence_technology_forums/f/custom-ic-design/64705/issue-with-level-3-mos-model-in-spectre/1405051"]So this is something that is different even though we are importing a Spice model I did not know that the Spice defaults are not known by Spectre[/quote] The challenge is that the very many SPICE implementations have varied since the first versions from Berkeley 50 years ago. The major differences tend to be between those that focus on integrated circuits (which was, after all, the original purpose of SPICE (Simulation Program with Integrated Circuit Emphasis) such as HSPICE, Spectre, AFS and those which focus on discrete designs such as PSPICE, LTSPICE and the newer QSPICE (of course, there are many others in both camps). Foundries tend to produce models characterised for Spectre or HSPICE - these do have differences here and there but are usually relatively small. MOS models in the IC world would never rely on a default value of W or L, often because in many SPICE simulators it is configurable. SPICE 2G6 and HSPICE have the .OPTION DEFW/DEFL and in HSPICE I believe the defaults are 100u for each. The use of the "B" prefix is a classic example of the deviation between SPICE variants. SPICE3 (I think) introduced behavioural sources with B (and LTSPICE/QSPICE follow that), whereas HSPICE used B for IBIS (and Spectre supports that in SPICE mode). Spectre is not based on the same code as Berkeley SPICE, and so has never just inherited the same settings as SPICE. It doesn't have DEFW/DEFL options and you normally never see MOS instances without specified W and L. In the discrete world of course, the W and L of the transistor is within the device and probably not that useful to expose, so the parameters for the model may have been normalised to the simulator default (maybe 1 for W and L, I'm not sure) but also some of the other parameters may have different defaults too in the models. Given that I don't have access to QSPICE (in fact its existence was news to me, although I think the author is the same as for LTSPICE so I'd expect them to be similar in modelling conventions), comparing the differences between the defaults and model implementation is hard. With PSPICE, we can handle that with Spectre since we have the detailed knowledge of how that differs from traditional SPICE. Spectre's SPICE language tends to follow SPICE 2G6/HSPICE conventions for the most part. [quote userid="472875" url="~/cadence_technology_forums/f/custom-ic-design/64705/issue-with-level-3-mos-model-in-spectre/1405051"]If I create a Pspice cell view would that be equivalent to pspice_include?[/quote] Yes. You'd see that the contents of the pspice view would get included into the netlist via a pspice_include automatically when netlisted. Regards, Andrew
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Forum Post: RE: Issue with Level=3 MOS model in Spectre
Thank you very much for the detailed response Andrew. My knowledge about the difference between Spice and Spectre is all from Ken Kundert's excellent book - "The Designer's Guide to Spice and Spectre" but didn't know about these details. This is good to know. Yes Qspice is also made by Mike Engelhardt the author of LTSpice. It is fairly new but is much more versatile and has some very impressive features like making subcircuits in C and verilog easier.
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Forum Post: RE: Issue with Level=3 MOS model in Spectre
One follow up question. I do see external models for Pspice which are encrypted. Would those be workable in Spectre? What would be the process to import them?
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Forum Post: RE: Allegro skills
I think he is looking for something like 'tbx postproc'
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Forum Post: Mastering Turbine Mark-II Meshing – A Step-by-Step Automation Guide Using Fidelity Python API
In this case study, we will be examining the meshing workflow process for a turbine nozzle guide vane, specifically the Mark II model. The primary objective is to demonstrate the capabilities of the Fidelity Python API script in accurately generating a mesh for a 2D high-pressure turbine blade. Through this example, we intend to illustrate how the API can efficiently manage complex meshing tasks, providing users with valuable insights into various key meshing parameters. https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1OPP000000sTWU2A2&pageName=ArticleContent
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Forum Post: RE: CDF: Modifying the cyclic type cdf choices for a specific instance of the PCell changes the choices for all the instances
Andrew, Thanks a lot for your time in responding. Got the point from what you said. It worked with a call back function in formInitProc. - Naveen
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Forum Post: RE: How to get pin position and location?
Morgan Please find below code for getting pin position(Left, Right, Top, Bottom): proc lGetPinPos {lPin} { set lStatus [DboState] set lPinName [DboTclHelper_sMakeCString] $lPin GetPinName $lPinName set PinName [DboTclHelper_sGetConstCharPtr $lPinName] # set lSelObj [GetSelectedObjects] # set lSelloc [] set lPinHOtSpotCP [$lPin GetHotSpot $lStatus] set lPinHOtSpotCPx [DboTclHelper_sGetCPointX $lPinHOtSpotCP] set lPinHOtSpotCPy [DboTclHelper_sGetCPointY $lPinHOtSpotCP] #get the location point set lStartCP [$lPin GetStartPoint $lStatus] set lStartCPx [DboTclHelper_sGetCPointX $lStartCP] set lStartCPy [DboTclHelper_sGetCPointY $lStartCP] if {[expr {$lStartCPx - $lPinHOtSpotCPx}] > 0} { puts "Pin $PinName is Left Pointed" } elseif {[expr {$lStartCPx - $lPinHOtSpotCPx}] 0} { puts "Pin $PinName is Top Pointed" } elseif {[expr {$lStartCPy - $lPinHOtSpotCPy}] < 0} { puts "Pin $PinName is Bottom Pointed" } } set lStatus [DboState] set lSelObj [GetSelectedObjects] set lIter [$lSelObj NewPinsIter $lStatus] set lNullObj NULL #get the first pin of the part set lPin [$lIter NextPin $lStatus] while {$lPin !=$lNullObj } { #placeholder: do your processing on $lPin lGetPinPos $lPin #get the next pin of the part set lPin [$lIter NextPin $lStatus] } delete_DboPartInstPinsIter $lIter
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Forum Post: 2 tests sim with different temperature
Hi,friends I have two tests, test1 and test2. Test1 needs to simulate only the 25°C value under the corner to obtain V1 , while test2 must simulate three temperatures (-40°C, 25°C, and 125°C) under the same corner as test1, using V1 as an input parameter from test1. How can this be implemented? like below： -40 test1 corner1 25° => get V1 =>V1 as input: test2 corner1 25° 125
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Forum Post: Logic Gates Circuit -to- VHDL -to- IC ??
Hi everyone i hope you are all doing well im a schematic Entry designer. i design, create and draw logic gates/Flip Flops circuits using NI Multism PLD desinger, and then export that design into a VHDL file and synthesize in a FPGA IDE for real FPGA simulation. - This an example of a digital button de-bouncer Now i after i confirmed that circuit is working i want to create an actual IC out of it (or ASIC ) but before manufacturing and chosign the fabricator, i have to create the transistor-level layout or photo mask (i actually don't know what that file called) and i heard that Cadence can do that but : - Does Cadence support pure digital logic design, and which version of Cadence do i need? - Do i have to start from scratch (rebuild it all manually) or just convert my VHDL file into that " transistor-level layout design" any suggestions or information will be appreciated Thank you for your time
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Forum Post: RE: Issue with Level=3 MOS model in Spectre
Yes, encrypted PSPICE models are supported, see page 9 of https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000056SHEAY (PSPICE is also a Cadence product).
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Forum Post: RE: Source Library Modification
Option 1: If there aren't many components in the cache, you could do a manual cache replace: Option 2: If applicable, you can replace the lib path as shown below: Option 3: a bit tricky and I am not sure this solves your problem, edit the Capture.ini file, located in your work folder (cdssetup is located where your pcvenv is also located) allegroWork\cdssetup\OrCAD_Capture\23.1.0 places to look at: [Part Library Directories] dir0=Q:\MYLIBRARY\ORCADCIS\SYMBOLS\ [Part Selector Configured Libraries] Number of Configured Libraries=2 Library0=Q:\MYLIBRARY\ORCADCIS\SYMBOLS\ADK_TEST.OLB Library1=C:\CADENCE\SPB_23.1\TOOLS\CAPTURE\LIBRARY\TRANSISTOR.OLB [Allegro Footprints] Dir0=Q:\MYLIBRARY\Data\... Dir1=Q:\MYLIBRARY\Data\... Dir2=Q:\MYLIBRARY\Data\... Dir3=Q:\MYLIBRARY\Data\...
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Forum Post: RE: Copy cline to solder mask layer
Hi Rohit Take a look at this:- How to create voids for critical signals in adjacent layer shapes
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Forum Post: RE: 2 tests sim with different temperature
Hi, This can be done setup using calcVal function in Assembler. The picture below shows the two corners you describe (the only difference between corner1 and corner2 is temperature). In the same Corners setup form, test1 is enabled to simulate only with corner1 and test2 with corner2. You can also see how calcVal is used in Test2 to read an output called 'V1' from Test1. Saloni
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Forum Post: RE: Issue with Level=3 MOS model in Spectre
Also, I tried using your model within a file (e.g. myModel.psp) and including it via pspice_include (ii.e. Pspice Files on Setup->Simulation Files). I see that doing this changes the default W and L to 100u and also alters the mobility value (u0) - so there is some difference in the modelling too (it adds a pspice compatibility flag). Doing that gives me this graph for the current: That appears to be what you're expecting. Maybe using the model you have with the B changed to I for the behavioural source might be enough for it to work - if you use it as a PSPICE model. However, getting an official PSPICE model would be better still. Andrew
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Forum Post: Understanding the Importance of Bypass Capacitors in Electronic Circuits
Hey fellow electronics enthusiasts, Have you ever wondered how you can minimize noise and spikes in power supply lines? Or how you can provide a stable and clean DC signal to your integrated circuits? The answer lies in the use of bypass capacitors. In this post, based on my experience, I will share functions, applications, and characteristics of bypass capacitors. I will also evaluate why they are a crucial component in many electronic circuits. Feel free to comment below so that this community can benefit from this information. What is a Bypass Capacitor? A bypass capacitor is a capacitor that filters out an AC noise from a DC signal, thus producing a cleaner and more stable DC output. It essentially shorts AC signals to ground, thus allowing only the DC component to pass through. This process is called ‘bypassing’ the AC noise; hence, the name ‘bypass capacitor’ is given. How does a Bypass Capacitor Work? A bypass capacitor is connected between the power supply pins (VCC and GND) of an integrated circuit. When an AC signal is present on a DC supply line, the capacitor acts as a short circuit and bypasses the AC noise to ground. For DC signals, the capacitor behaves as an ‘open circuit’, which lets the DC component to pass through to the integrated circuit. What are the Key Functions of a Bypass Capacitor? · Noise Reduction: A bypass capacitor reduces both power supply noise and spikes on the supply line. · I mmediate Current Demands: I t provides immediate current demands of an integrated circuit whenever it is switched on. · DC Signal Filtering: It filters out AC ripples from the DC signal, thus producing a clean and stable output. What are the Necessary Characteristics of a Bypass Capacitor? · Low Impedance: A bypass capacitor should have low impedance to effectively filter out the AC noise. · Good Charging and Discharging Capability: It should be able to charge and discharge quickly to respond to the changes in the supply line. · Effective Noise Reduction: It should be able to effectively reduce noise currents and provide a stable DC output. · Good Grounding: It should be able to capably ‘ground’ the noise current. So, What’s the Conclusion? In conclusion, bypass capacitors are a crucial component in many electronic circuits; they provide a stable and clean DC output by filtering out AC noise. When selecting a bypass capacitor, it is essential to consider its series inductance value and distribute the bypass elements throughout the PCB to ensure effective noise reduction.
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Forum Post: RE: Custom Colour Save
Hi MR20250507523 , We cannot save a color palette in Presto but if you assing a color to net or other objects, save the view from visibility tab and if you reload the view the assigned colors whould be visible. Let me know if you are not seeing the same
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Forum Post: RE: Source Library Modification
AK20250513568 Please follow below article it will helps to replace design cache library to new location. Article (20512519) Title: How to update the design cache library path to a new library path URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009mMUXEA2 Hope it helps.
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Forum Post: RE: How to add vertex to trace
Hello anowack , currently there is no option in Presto to add vertex. I know there are functioality requests in Cadence Support platofrm to add this.
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