Hi, I have written a script that adds the net names on pins to the Package Geometry silkscreen layers. However, when the Allegro (v16.6) silkcreen command is run, the text is not transferred to the autosilk layer. Other text on this layer is ok. I am using the following command to add the text: axlDBCreateText( sprintf( nil "%s" symPinNet ) , symPinPosn , textOrientTop , "PACKAGE GEOMETRY/SILKSCREEN_TOP" , symbPin ) The text adds successfully on the board and is attached to a pin with a rubber band. Is there something I should do to make this text transferable? Thanks,
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Forum Post: Text added to pins does not get added to autosilk layer
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Forum Post: RE: Transferring user defined property values between Capture and Allegro PCB Editor
It's not going to work at symbol (dra) level because the symbol is not netlist aware. Once you have imported the netlist into the board try the Display - Properties command and you should be able to see the properties you have added. You have to do this on a design by design basis.
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Forum Post: How to change design for ADE XL/Assembler test using SKILL and preserve analysis, variables and outputs
Hi, I need to change the design for ADE XL/Assembler test using SKILL. I am tryed to do this as folowing: testSession=axlGetTest(axlGetMainSetupDB(axlGetWindowSession()) "aa") toolargs=axlGetTestToolArgs(testSession) rplaca( cdr( assoc( "view" toolargs ) ) "schematic" ) axlSetTestToolArgs(testSession toolargs) This indeed changes the design but also resets analysis, variables, and outputs. Is it any other way to change the design without resetting analysis, variables, and outputs? Best regards, Alex.
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Forum Post: RE: How to change design for ADE XL/Assembler test using SKILL and preserve analysis, variables and outputs
Hi Alex, There's a CCR (number 1271081) for this - although sometimes I see it works, sometimes it fails. Not quite sure why. I suggest you contact customer support asking for a duplicate to be filed to increase the priority. Since you're talking about Assembler, maybe instead you can use maeCreateTest and use the ?sourceTest to import an existing test with a new design, and then delete the original test. I didn't test this, but it may be a workaround. Regards, Andrew
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Forum Post: capture to pdf_tool crashes
In one user PC with OrCAD 17.2 (having latest ISR28) when he chooses File-Export PDF, the tool crashes(before opening PDF Export window) with message as "the application has quit unexpectedly" . Tried renaming home variable from 17.2.0 . The OrCAD PS_17.2 driver is installed in printers. What might be the reason for the crash. Issue happening across all designs.
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Forum Post: RE: How to change design for ADE XL/Assembler test using SKILL and preserve analysis, variables and outputs
Hi Andrew, I tried maeCreateTest with ?sourceTest and ?view "newviewname". It doesn't work. Test created with the same design. So I suppose it is no workaround and I need to save analysis, variables, and outputs, then change the design, then set analysis, variables, and outputs. I generally have an idea how to save and then create variables and outputs. Can you please suggest how to save a list of analysis and then add them to test? Thank you, Alex.
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Forum Post: RE: How to change design for ADE XL/Assembler test using SKILL and preserve analysis, variables and outputs
Alex, I didn't read the documentation carefully enough. Looks as if using ?sourceTest just creates a copy of each test but doesn't change the lib/cell/view in the process. Any workaround is likely to get a little complicated, so please log a case with customer support as I suggested earlier, as I suspect it will take more time than I have at the moment to investigate. Regards, Andrew.
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Forum Post: Gain of a Charge Pump in Phase locked loop
Hi, I made a charge pump for 1GHz PFD up and down signal pulses. I am interested in finding out the gain of Charge Pump. Can anyone guide me the good reference or some idea about its procedure? Thanks,
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Forum Post: change instance name in schematic
It is a very simple question, it seems that I can't change an instance name by "q" it in schematic window. I have to go to the property editor and change it there. For instance, I placed a resistor R1 in the schematic and then later I want to change it to R1 . Naturally I want to q it and then change it there. however, the instance name field is grey. Instead, I have to change it in the property editor. For some reason, changing things in the property editor can be annoying. I click in the field that I want to change, sometimes when my cursor moves, then immediately the edit mode is gone, I have to click again and again. I don't know why it is happening. Is there a way that I can edit the instance name by q it in schematic, or how can I fix the input issue in the property editor? I am using IC617. Thanks!
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Forum Post: RE: Creating all pin symbol containing inherited power\ground connections
Typically I'd expect the inherited connections to become explicit once layout has been done - effectively you've "hardened" the connections. It's not clear which inherited connections you're talking about - if it was to the leaf components, I'd expect you to have them connected to real power connections. If it was for the extracted block itself, then it may just be that you haven't got pins on your layout view with the netExpressions on. Wasn't clear which extraction tool you're using either? Andrew.
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Forum Post: RE: change instance name in schematic
I've never seen the instance name field disabled like that. Sometimes the lib name or cell name fields (by some customisation) but I'm not sure why the instance name field would get disabled. I can't see anything in our code that does this. So it might be some customisation which went wrong - worth contacting customer support to see if you can track it down. Probably just typing: hiSetFieldEnabled(schObjPropForm->instanceName t) in the CIW will re-enable it. Don't know why you're having problems with the property assistant - worth talking that through with support too. Regards, Andrew.
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Forum Post: RE: Distributed Processing Library command line
Dan, Not something I've played with - probably best to contact customer support . Andrew.
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Forum Post: RE: LEF generation from abstract is missing class,symmetry, origin information
Seems odd. How was the abstract view created?
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Forum Post: RE: Creating all pin symbol containing inherited power\ground connections
Hello Andrew, Sorry for not providing the details related to the extraction tool and inherited connections. Let me clarify them first. The extraction tool I am using, is PLaSMa. Here for extraction I am selecting StarRC. Let me explain now the steps I followed. I drew a schematic where I used vdd_inherit, vdd1_inherit, gnd_inherit, gnds_inherit from STlib library. A symbol is generated from the schematic cellview, which I used in the testbench for the testing purpose. Once the circuit schematic is complete, I drew the layout. In the layout, I used explicit pins for the power rails. Once, the DRC and LVS results are clean, I went for extraction. The extracted netlist is used while running the same testbench. I selected the 'extracted' option in ADE for that. Now, I see the simulation result is way too far from the actual output. While debugging, I realised that the extracted netlist cannot find vdd, vdd1 and gnds. Please let me know whether there are points which I still missed out. Regards Saikat
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Forum Post: RE: LEF generation from abstract is missing class,symmetry, origin information
HI Andrew, Abstract view was manually created by copying the pins from layout and placing it in a new view. Apart from pins abstract view had PR boundary and metal blockage layers (created as objects). The pins & layers are placed in same location as in layout. Regards Anand
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Forum Post: RE: Creating all pin symbol containing inherited power\ground connections
Saikat, I don't know what PLaSMa is (never heard of it). However, StarRC is a Synopsys tool, so the problem may be how StarRC is generating its extracted views - you would need to contact Synopsys about that, or ask on one of their forums. If it's not in the extracted netlist, it's probably not in the extracted view either - so most likely the issue is related to how the extracted view is generated. Regards, Andrew.
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Forum Post: RE: LEF generation from abstract is missing class,symmetry, origin information
Probably the simplest would be to use the abstract generator to build the abstract, but I suspect it's just that you're missing some cellView attributes and a prBoundary object. First edit the cellView properties (File->Properties) and fill in the CellType (I suspect yours is "none") - this sets the CLASS, and the Symmetry Type (this sets Symmetry in the LEF): Then you need a prBoundary object (not a shape on the prBoundary/drawing layer, but an actual object, as created by Create->P&R Objects->P&R Boundary Without this I get some pretty clear warnings in the CIW: WARNING: (OALEFDEF-90016): Design ADDFHX1 abs1 does not have a snapBoundary. Searching for a prBoundary. WARNING: (OALEFDEF-90017): Design ADDFHX1 abs1 does not have a prBoundary. Searching for a layer-purpose pair. WARNING: (OALEFDEF-90018): No shape on layer purpose pair found in the design ADDFHX1 abs1. The ORIGIN, FOREIGN, and SIZE statements will not be printed. Ensure that you have defined the snapBoundary, PRBoundary, or geometry on LPP (boundary, boundary) in the cellview. With it, I do get the ORIGIN, FOREIGN and SIZE entries. I do find that if you have the prBoundary/boundary layer purpose, it still works, although that's really not the supported flow nowadays. If you've used a different lpp (e.g. prBoundary/drawing) then it doesn't work and you get the warnings above. Regards, Andrew.
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Forum Post: RE: LEF generation from abstract is missing class,symmetry, origin information
Hi Andrew, I followed your instructions and is working fine now. Thank you very much. Regards Anand
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Forum Post: RE: Creating all pin symbol containing inherited power\ground connections
Dear Andrew, I used Quantus QRC extraction tool as well. The problem was same. I found the following solution suggested by you. https://groups.google.com/forum/#!msg/comp.cad.cadence/j9JmVQv2TQY/19ROP1v-Y88J I tried following the same. However, there are some differences in the options as I am using a different version of the tool. But I am not successful with this. My final goal is to have a symbol where I will have all the inherited connections as pins, even if the inherited connections are used in the schematic. I have given the following example which I would like to achieve. Regards Saikat
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Forum Post: gpdk045 vth at dcop is not same as model spec
Hi, Andrew I have checked the gpdk045 model report, it's said the vth is obtained using constant current method, the intercept current=Icon*W/L (Icon=1e-8A for 1.1V device and Icon=1e-7A for 1.8V device), Vth unit is V, spec is here and i simulated use the circuit, VDS=1.1V and sweep the VGS from 0 to 1.1V. according to the equation constant current method int current = 10u/40n *1e-8A =2.5*e-6 A =2.5uA, check the ids and vth is located at around 320mV, close to the spec, but check at result browser, plot the vth, about 620mV, what is wrong here? thanks a lot.
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