Hello Andrew, Glad to know I'm in the right track. I am using 6.1.7-64b.500.9. So until an update rolls out, I have to stick to hiRegTimer()? Best regards, Karam
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Forum Post: RE: Plot expression after ADE-XL run
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Forum Post: Display current view in window title bar
Hi, Is there a way to have the window's title bar display the current view? I ask because we use Keysight's Momentum with Virtuoso and it keeps a separate layout view which is essentially identical to the standard layout. The issue is that there is no way to tell which view is currently open when you have two layout (one "layout" layout view, one "momentum" layout view) views open at one time. Is there a way to enable this?
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Forum Post: RE: Plot expression after ADE-XL run
Karam, The issues I'm thinking of should have been resolved by the version you're using, so please report this to customer support . Probably using the timer is the only workaround in the meantime (I'm assuming adding ?enableLegend t doesn't make a difference - I wouldn't expect it to). Of course it would be worth checking with a later hotfix first in case it got fixed and I just didn't find a report of the issue (the latest is IC617 ISR16). Regards, Andrew.
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Forum Post: RE: Display current view in window title bar
Er, that's exactly what it does do - shouldn't need to do anything to enable this. Maybe the Keysight Moment interface is opening the window and explicitly setting the banner? Regards, Andrew.
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Forum Post: RE: Display current view in window title bar
Hi Andrew, All of our windows just say "Virtuoso". It's an issue with our setup then. Good to know that's the intended behaviour. Regards, Matthew
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Forum Post: RE: Plot expression after ADE-XL run
I tried adding ?enableLegend t but it didn't help. To be fair, the legend box is captured in the image, only the text (and line color indicator) is missing. I would have been satisfied if it was the other way around, though. Best regards, Karam
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Forum Post: RE: which shape type (dynamic/static) to be used in negative power planes?
Negative planes still have their place in some designs and if you continue to use them I would recommend using Dynamic shapes. Why? Dynamic shapes will automatically void any Route Keepouts on the layer (For example, Keepouts around mounting holes) while pins and vias will continue to use geometries defined in the Padstack. Hope this helps, Mike Catrambone
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Forum Post: RE: hbnoise: difference between sweep-type relative harmonic=0 and absolute
Hi Andrew, Thanks for your reply. I escalated this inside my company. My colleagues from the methodology department is tackling the issue. They will probably escalate it to Cadence support team. Thanks for your time! Best regards, Ahmed.
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Forum Post: Predefined Ports in Virtuoso
Hello, i have a question regarding the predefined ports in virtuoso. I noticed that stdout and poport are equal, so what is the difference between stdin and piport ? My guess is that piport is linked to that "what you write in the CIW", whereas stdin is the "default" UNIX stdin !? If so, is it possible to redirect stdin to piport ? Thanks in advance. Best regards, Matthias
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Forum Post: Cross Section Editor Impedance Calculator
Hi All, I am trying to use the impedance calculation in the Cross Section Editor. I have compared the results to other impedance calculators. Three different calculators give very consistent results, while the results from the Cross Section Editor differ greatly. Attached are screen shots from the Editor and Saturn PCB Design's Toolkit. The Saturn Toolkit results match the other two calculators I tried. Looking at the TOP layer, the single ended impedances are different, and the differential impedances are very different. Should the dielectric constant for the top layer be 4.5? I read in another post that it should be 4.5 for the internal layers because the prepreg squishes around them, but what about the top? Dropping it to 3.33 brings the single ended impedance close to the other calculators, but not the differential. Why should that dielectric constant matter at all? So, the question is: Why should I use/trust the CSE calculator when 3 others give consistent different results? Thanks or any insight you can give!
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Forum Post: RE: ADE XL Timed Out Running Monte Carlo Simulation
Hi Andrew, Thanks for the reply. I believe I may have some compatibility issues with my installation. We are running IC6.1.7-64b.78 on RHEL 7.2 Linux 3.10.0-327.36.1.el7.x86_64 x86_64 Besides the Monte Carlo issue, I cannot see Assura in my Layout XL menu listing. We have installed ASSURA41 and EXT172. I don't see that Assura415 is supported on RHEL7. Do I need to revert to a different OS in order to use all these tools I have available ? thanks, jill
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Forum Post: RE: Predefined Ports in Virtuoso
Matthias, stdin is the stdin of virtuoso (i.e. the terminal window) whereas piport is the CIW input. You can reassign stdin=piport if you really want. However, reading from either stdin or piport is a fairly unusual (and probably not recommended) thing to do with Virtuoso. Andrew.
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Forum Post: RE: ADE XL Timed Out Running Monte Carlo Simulation
I'm not sure this would cause Assura not to appear in the menus, but maybe you've downloaded the wrong Assura version. First of all, I would suggest you install a more recent IC617 - you've got the base version. I'd suggest you install the latest hotfix of IC617 and ASSURA 41: That does support RHEL7 and is rather more recent. Regards, Andrew
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Forum Post: RE: Display current view in window title bar
Hi Matthew, What window manager are you using? I've seen (I think) in the past some issues where the window banner gets truncated because of not understanding the registered trademark (i.e. ® ) character after Virtuoso. Regards, Andrew.
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Forum Post: RE: Display current view in window title bar
Matthew - one thought in case that is it. Try doing this in the CIW and then opening the windows: envSetVal("designEditor.window" "windowNameFormat" 'string "%m: %l %c %v %x %a") It's the "%a" that adds the application name. Note that you have to include it somewhere otherwise it gets automagically added to the beginning again (so I just put it at the end). Regards, Andrew.
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Forum Post: Parasitic exclusion
Hello, I was using parasitic filter from an extracted view to discover the worst influences. I understood that I could add some parasitics or include all parasitics of an extracted view. So, if I want to simulate my circuit with all parasitic excluding a net, I have to include all parasitics in my constraint window and deactivate the one I don't want. Logic. But, it would be more simple in this case, by default activating all parasitics (without including the long list of parasitcs) and only put in my constraint window the net I don't want the parasitics. Is it possible? Emmanuel
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Forum Post: How to do UVM transaction recording with irun?
Can anyone explain step-by-step how to record transactions in irun? e.g, what to do in UVM source code, which options for irun and etc.?
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Forum Post: RE: What is default port order, and how to create it?
So for everyone who confused with portOrder and CDF termOrder that is what I was able to figure out. portOrder property Each view can have portOrder property. Schematic and symbol views, when created from scratch, created without portOrder property. Text views as VerilogA VerilogAMS etc. created with portOrder property also when created from scratch. When cell view created using "Create Cellview from Cellview", portOrder property created on new(created) cellview (Article 20302001). If schematic or symbol created from text view (VerilogA etc.) using "Create Cellview from Cellview", The portOrder property will be set according to the order of ports in the definition of source text view. If symbol created from schematic view using "Create Cellview from Cellview", portOrder property will be set as follows: Default portOrder is: output/inputOutput/input when for each type ports alphabetically sorted (Article 20302001) CDF termOrder property CDF can have termOrder property for each simulator If "auCore.misc" "createCDFtermOrder" set to t (default) CDF termOrder will be created automatically for all simulators when schematic view created. Default order of ports is alphabetic Spectre netlisting If neither CDF termOrder property for Spectre, nor portOrder property of a schematic set, the alphabetic port order will be used by netlister. If it is only CDF termOrder property for Spectre, this termOrder will be used by netlister If schematic view (or another used view) termOrder is set, it will be used regardless of CDF termOrder property Verilog-AMS netlister Seems to always use output/inputOutput/input port order regardless of CDF termOrder or portOrder property. Views creation When text view (VerilogA etc.) created from a schematic using "Create Cellview from Cellview", ports created in flowing order: If portOrder property isn't set, default portOrder will be used ( output/inputOutput/input when for each type ports alphabetically sorted) If portOrder property is set, port order from portOrder property will be used SKILL functions almGetTerminalList(lib cell ?tool simulator) Can be used to read CDF termOrder property for specific simulator schGetPinOrder() If portOrder property isn't set, function will return default portOrder ( output/inputOutput/input when for each type ports alphabetically sorted) If portOrder property is set, function will return port order from portOrder property artGenerateHierSymbolCDF() Function will reset CDF termOrder property for all simulators to alphabetic, same as created authomatically if "auCore.misc" "createCDFtermOrder" set to t
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Forum Post: Term net name changing for the pins automation using SKILL code
Hello, I am on Virtuoso IC6.1.7 I want to change by SKILL code the pins net names for a certain block. I use in my code something like : [..] term->net->name = "new_value" and I get an dbSetq error (DB-370034) N.B. term~>name I can change with no problem, but it does not help me. Somehow this property value cannot is read-only. How can it be changed automatically? Can anyone tell help me on this one? Thank you, BR, Odin
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Forum Post: Code coverage for sv verification envrionment
I referred to the link below but it seems it is much a historical solution. Now I am trying on IES 15.023. So is it possible to generate code coverage for sv verification environment with irun? Thanks. https://community.cadence.com/cadence_technology_forums/f/functional-verification/9140/generating-code-coverage-for-sv-verification-environment
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