HI Andrew, There is any skill code for via to via conversion i.e;m2_m1c to m3_m2c.So please let me know is there any solution for it and we are using virtuoso 6.1.6-64bit version. Thanks in advance, Prabhu kumar.A.
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Forum Post: RE: Stacked Vias
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Forum Post: RE: Stacked Vias
Clearly you didn't read the forum guidelines as you posted in the middle of an 8 year old thread with a question that was only tangentially related to the original question. That said, I'll forgive you as I see that they don't seem to be pinned to the top of the list of posts any more (I'll check why). If you're asking about replacing one via with a different one, you have to delete and recreate the via (presumably with similar parameters). There's no built-in function to do that (as far as I know) and I've not written one myself. Of course you can delete (using dbDeleteObject()) and recreate (using dbCreateVia), but nothing to do all of this automatically in one shot. Regards, Andrew.
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Forum Post: RE: "Attribute "CDS_DI_CONTROL_MASK" is not defined." Allegro HDL crashes
Thank you very much, it worked. I installed the latest hotfix and I can now open the project again.
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Forum Post: RE: Custom "window"-ed form, assign "Enter" for specific callback.
Hi Andrew, " Enter" definition works only if numpad Enter key is used. It does not work with main Enter key for me either. Sadly, I'm not able to mimic the event when main "Enter" key is pressed in SKILL API Finder window. Judging by its behavior the CB ( startSearch ) is associated with "Find what" ComboField and "Go" Button e.g. you can trigger the callback only if one of those fields is at focus. Nor hiCreateCombField or hiCreateButton posses arguments which could mimic this functionality. ( Yes, hiCreateComboField has ?focusInCallback , but it's triggered immediately when field gets in focus. ) hiCreateButton ( ... ?callback g_callback ... ) hiCreateComboField ( ... ?callback g_callback ?modifyCallback g_modifyCallback ?focusInCallback g_focusInCallback ... ) There should be way to trigger a CB in window form when those two criteria are met: 1) Field in focus & 2) Main Enter Key is pressed
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Forum Post: RE: Synthesis Area plus power estimate concatenation
Thank you very much for the reply, I will work on the information you gave me. However to clarify your confusion: [quote userid="384090" url="~/cadence_technology_forums/f/high-level-synthesis/38293/synthesis-area-plus-power-estimate-concatenation"] read_hdl -sv -library WORK ../vlog/blocks0001.v set DESIGN block0001000 elaborate $DESIGN check_design -unresolved $DESIGN set input_port_list { a } set output_port_list { y } synthesize -to_generic -effort high $DESIGN synthesize -to_mapped -effort high $DESIGN set area_design [get_attribute area $DESIGN] set out [open "../rpt/blocks0001.rpt" w] puts $out "Total gate_count $DESIGN : $area_design" close $out read_hdl -sv -library WORK ../vlog/blocks0001.v set DESIGN block0001001 elaborate $DESIGN check_design -unresolved $DESIGN set input_port_list { a } set output_port_list { y } synthesize -to_generic -effort high $DESIGN synthesize -to_mapped -effort high $DESIGN set area_design [get_attribute area $DESIGN] set out [open "../rpt/blocks0001.rpt" a] puts $out "Total gate_count $DESIGN : $area_design" close $out .... and so on *************************************************************** [/quote] blocks0001.v is a verilog file that contains 1000 modules . The first one is block1000 the last one is block1999 . For this reason the script reads from the same file and every time changes the $DESIGN, synthesize and the print the area on a file. If I do the same with the power I get [quote userid="384090" url="~/cadence_technology_forums/f/high-level-synthesis/38293/synthesis-area-plus-power-estimate-concatenation/1353682#1353682"]Error : Multiple designs are available. Specify the design you want to use. [TUI-17] [::report::power::report_power] : There is no unique design here. :Specify a design by using the cd command to change to that design's directory or specify the design as an argument for the command. Failed on find_unique_design[/quote]
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Forum Post: Statistical Contribution or criticality of each device
Hello, Suppose we are running a Monte Carlo simulation & we are interested to find which MOSFET device is critical, is it possible to find out every MOSFET's contribution to criticality of mismatch, like how we get in a 'Noise Summary' for a noise simulation ???? Thanks in advance
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Forum Post: How to properly handle wave family in custom calculator function
Hi, I needed a function that will resample waveform using points from another waveform. So I wrote function below: ;Function to resample sourceWave by points from pointsWave ;sourceWave waveform to be resamled ;pointsWave from this waveform points taken to resample sourceWave procedure( resampleByWave(sourceWave pointsWave) let( (xVec yVec wave yFactor numOfPoints thisX sweepVal i sweepName sweepValues currentSourceWave currentPointsWave sweepValType) cond( (drIsWaveform(sourceWave) ;printf("%L\n" sourceWave->??) wave=drCreateEmptyWaveform() xVec=drGetWaveformXVec(pointsWave);x vector created from pointsWave numOfPoints=drVectorLength(xVec) yVec=drCreateVec(drType(drGetWaveformYVec(sourceWave)) numOfPoints);empty y vector for( i 0 sub1(numOfPoints);for each point from pointsWave thisX=drGetElem(xVec i);x value currentValue=value(sourceWave thisX );y value from sourceWave corresponding to x value from pointsWave drAddElem(yVec currentValue);add y element );for drPutWaveformXVec(wave xVec) drPutWaveformYVec(wave yVec) wave~>leafSignalTypeName=sourceWave~>leafSignalTypeName wave~>leafDataSet=sourceWave~>leafDataSet wave~>leafAnalysisType=sourceWave~>leafAnalysisType );drIsWaveform(sourceWave) (famIsFamily(sourceWave) sweepName=famGetSweepName(sourceWave) sweepValues=famGetSweepValues(sourceWave) sweepValType=type(car(sweepValues)) case(sweepValType ('fixnum wave=famCreateFamily(sweepName 'intlong)) ('flonum wave=famCreateFamily(sweepName 'float)) ('string wave=famCreateFamily(sweepName 'string)) (t error("resampleByWave: unable to understand type %L\n" sweepValType)) );case foreach( sweepVal sweepValues currentSourceWave=famValue(sourceWave sweepVal) currentPointsWave=famValue(pointsWave sweepVal) famAddValue(wave sweepVal resampleByWave(currentSourceWave currentPointsWave )) );foreach );famIsFamily(sourceWave) (t error("resampleByWave: invalid waveform %L\n" sourceWave) );t );cond wave );let );proc I am not sure about a case when input waveforms are family of plots. Is this part of the code correct?
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Forum Post: PhysConfig: force to descend
Hi, How can I set an instance to "force to descend" in skill. so during the "Gen from source", it will generate the sub layout of that instance. Thanks
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Forum Post: Feature Request: New 3D Engine PCB 17.2
Hello, this is my first post to this Forum. hopefully it is okay? I use the new new 3D Engine with the Cutting function and it is very importend to add any mirror function for the cutting. as Sample if you cut the z-axis and you have mounted a hausing at the bottom side then you Need to slide starting from bottom. Hopyfully i have explaind so you can understand my wisch. Thanks Peter
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Forum Post: RE: Synthesis Area plus power estimate concatenation
Hi GioFz, I am wondering if you have access to the documentation. No being impolite - just asking :-) You can locate the PDF file in the installation directory of the tool or use the cdnshelp command in a terminal window. report power should have a design object that tell the tool where it is in the virtual design directory. From the documentation : Reports the power consumed. The information returned depends on your current position in the design hierarchy and on the specified objects. If no objects are specified, the report is given for the design or instance at the current position in the design hierarchy. You should be able to do the following by surrounding the report power command with the virtual cd command that works in the synthesis tool. cd /$DESIGN report power cd / You could also use the TCL script I gave as a starting point to go through the design hierarchy that has the 1000 modules, and iterate over each one automatically in the loop just for the report power command. Please do share more information - if you had explained that you had 1000 modules - we would have got here quicker! ;-) Don't be shy to share information, especially if it will help us help you! :^) J
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Forum Post: RE: How to properly handle wave family in custom calculator function
Your code is unnecessarily complicated in the famIsFamily branch. You should just be able to do: (famIsFamily(sourceWave) famMap('resampleByWave sourceWave pointsWave) ) This takes care of iterating through the families (you could have families, or families of families, or families of families of families - etc) and then applying the resampleByWave to the layer beneath and reconstructing the curves or families from that. Note, I didn't test your code (lack of indentation made it hard to read too); my suggestion is however the way I do this all the time. Andrew.
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Forum Post: RE: Statistical Contribution or criticality of each device
Yes. In ADE XL (it's actually an ADE GXL licensed feature) or in Assembler/Explorer (there it's a Virtuoso Variation Option feature) there's the "mismatch contribution' icon (which is a sort of circular icon towards the right end of the results icons). This computes the contribution of the mismatch variation of a device to the variation of the measured output. It's considerably more complicated than noise contribution. There is also the possibility to do this with dcmatch analysis, but that's then a dc sensitivity analysis rather than monte carlo - so you can't look at the contribution to arbitrary values. More details are in the Art of Analog Design blogs - in particular this edition (you might want to search in the community for "Art of Analog Design" for all of them). Regards, Andrew
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Forum Post: RE: Stacked Vias
[quote user="Andrew Beckett"]Clearly you didn't read the forum guidelines as you posted in the middle of an 8 year old thread with a question that was only tangentially related to the original question. That said, I'll forgive you as I see that they don't seem to be pinned to the top of the list of posts any more (I'll check why).[/quote] We've fixed the pinned posts so that the forum guidelines now are at the top of each forum. So there's no excuse for anyone not reading them now ;-) Regards, Andrew.
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Forum Post: RE: Blackbox pin after partition
I can answer it myself. Since I had many input pins connected to constant values, and some of them were moved during partition, I've tried to add the tie cells in the synthesis. This solved the problem. Still I don't understand why, but it worked.
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Forum Post: RE: How to properly handle wave family in custom calculator function
By the way, a similar approach is necessary for any custom function in order to work in ADE XL with sweeps, corners, and Monte Carlo (see https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=20467133 ).
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Forum Post: RE: Synthesis Area plus power estimate concatenation
Hi Jay Joshi, Yes I have access to the documentation. So sorry for my silly errors about that. I said that I had a lot of blocks to synthesize but I was not accurate to say clearly that all these blocks are defined as modules in one verilog file. I can understand that I was a little bit vague, however I was looking for a suggestion more than a problem solving. So, with all this information I could try to find a solution. By the way my initial request was about this : " set area_design [get_attribute area $DESIGN] set out [open "../rpt/blocks0001.rpt" w] puts $out "Total gate_count $DESIGN : $area_design" close $out " Which result is " Total gate_count block0001000 : 18.522 Total gate_count block 0001001 : 18.522 Total gate_count block 0001002 : 18.8748 Total gate_count block 0001003 : 18.8748 .....etc. " Every blockxxxxxxx is a modules in the verilog file. So I get one line only for each modules. What I was trying to achieve is the same thing but with the POWER. So something like that: "Internal power for block0001000 : 1 Internal power block 0001001 : 2 Internal power block 0001002 : 3 Internal power block 0001003 : 4.....etc. " Simple in words but I think not so easy in practice. Although it is so easy to get the area ([get_attribute area $DESIGN]) but not the internal/dynamic power? Thanks®ards, GioFz
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Forum Post: customizing ViVA result browser traces default settings
Hi, when the result browsre opens after a Simulation, all traces are "combined" in one graph. I would like to change the default settings, so that the traces are shown as "split strips" automatically. I found a solution in the forum thread "customize viva Strip", but this does not work in my case, and I do not know why. I tried both, the .cdsinit and .ecdenv commands. I am using virtuoso 6.1.7.500.14. Any idea ?
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Forum Post: Library Manager display settings
Hello, I defined in Library Manager -> Edit -> Display Settings, some custom settings. How could I change them? Is there an editable configuration file in which they are saved? Thank you Best regards, Aldo
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Forum Post: RE: customizing ViVA result browser traces default settings
Update: the .cdsinit command is working (after correcting a typo in the command) But the .cdsenv command is not working.
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Forum Post: line continuation symbol for the cds.lib file
Hello, is there a line continuation symbol for the cds.lib file? Thank you, Aldo
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