Hi Andrew first of all thank you for your replay. I use cadence 6.14 and calibre 2011, and tsmc 130nm technology. i need to how the process variation of nmos and pmos affect the frequency of the ring oscillator (5 inverters ), i will use this ring to make PUF for IOT applications. Regards, Amin
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Forum Post: RE: How to find frequency for ring oscillator in Monte-Carlo analysis?
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Forum Post: RE: How to properly handle wave family in custom calculator function
Alex, Yes, famMap will iterate over families in all the arguments together, so it will work pair-wise as you desire. The second question I can't really answer, as it almost certainly depends on what platform you're running your web browser on and which browser you're using. I use Mac and Safari (mostly) and Chrome (occasionally). I do from time to time have problems with preserving indentation - but I've not really done an exhaustive analysis of what works when (it has changed over time with different versions of the forum software too). Regards, Andrew.
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Forum Post: Innovus: Does not detect Inverters in library
Dear all, I'm using Innovus to P&R a design consisting of custom made cells. The cells have been characterized and compiled into a .lib file using Synopsys SiliconSmart. Everything works as expected, but I cannot do clock synthesis as Innovus does not detect my inverters as usable; Total number of combinational cells: 16 Total number of sequential cells: 2 Total number of tristate cells: 0 Total number of level shifter cells: 2 Total number of power gating cells: 0 Total number of isolation cells: 0 Total number of power switch cells: 0 Total number of pulse generator cells: 0 Total number of always on buffers: 0 Total number of retention cells: 0 List of usable buffers: Total number of usable buffers: 0 List of unusable buffers: Total number of unusable buffers: 0 List of usable inverters: Total number of usable inverters: 0 List of unusable inverters: Total number of unusable inverters: 0 List of identified usable delay cells: Total number of identified usable delay cells: 0 List of identified unusable delay cells: Total number of identified unusable delay cells: 0 My .lib file does not have cell footprints, according to the Innovus user guide this should be fine as it figures out the footprint automatically, depending on functionality. This is the output from 'reportFootPrint': # footPrint: INVX1 nrCell: 3 Library: Library: INVX1 INVX1 1 66.039 64.064 Y=(!X) INVX2 INVX1 2 32.803 32.654 Y=(!X) INVX4 INVX1 3 16.598 16.955 Y=(!X) # footPrint: INVX1 nrCell: 3 Library: Library: INVX1 INVX1 1 130.344 127.401 Y=(!X) INVX2 INVX1 2 64.316 65.580 Y=(!X) INVX4 INVX1 3 32.618 34.204 Y=(!X) Clearly, Innovus also sees that indeed it is an inverter and detects all inverters having the same footprint. Finally, I checked the 'dont_use' property, which is false. Hence the question, how can I further debug this, or even better, what would be the solution? (I am not allowed to upload the .lib files) Thanks.
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Forum Post: RE: resizing a schem symbol
Had the exact same problem. After selecting All bits and pieces including the bounding box many square dots became pink, showing objects that did not appear when downsizing the bounding box. I managed to strictly select those invisible lines and deleted them. I was then able to downsize the bounding box as desired. What puzzle me is how can one manage to insert invisible objects in a part? Whatever, problem solved. Thanks oldmouldy !
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Forum Post: RE: Change Pins from VSS to DVDD and vice versa in the Schematic
Hi Andrew The code is working fine. Thanks. Utkarsh
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Forum Post: RE: customizing ViVA result browser traces default settings
I added the following line to the .cdsenv: viva.rectGraph stripChartOn string "true" The .cdsenv is not located in my ~ Folder because I redefined the searchpath in "setup.loc" to my workarea via $CDS_WORKAREA. In the workarea there is the "csfLookupConfig", that defines to search for .cdsinit, .cdsenv and display.drf in the $CDS_WORKAREA folder. This mechanism works fine.
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Forum Post: same value for a RANDC variable of base class in extended class objects
i have a randc variable "index" in c_base . i've two new classes ( class_1 & class_2 ) extended from base_class. when randomizing the extended class objects, i observed the variable "index" is having same values in C1 & C2 objects. Below is the simplified copy of my code: class c_base extends uvm_sequence_item; rand bit [9:0] index; `uvm_object_utils_begin(c_base) `uvm_field_int(index,UVM_ALL_ON) `uvm_object_utils_end function new(string name="c_base"); super.new(name); endfunction endclass class class_1 extends c_base; rand bit [3:0] var1; rand bit [7:0] var2; rand bit [3:0] var3; `uvm_object_utils_begin(class_1) `uvm_field_int(var1,UVM_ALL_ON) `uvm_field_int(var2,UVM_ALL_ON) `uvm_field_int(var3,UVM_ALL_ON) `uvm_object_utils_end function new(string name="class_1"); super.new(name); endfunction endclass class class_2 extends c_base; rand bit [4:0] var4; rand bit [10:0] var5; `uvm_object_utils_begin(class_2) `uvm_field_int(var4,UVM_ALL_ON) `uvm_field_int(var5,UVM_ALL_ON) `uvm_object_utils_end function new(string name="class_2"); super.new(name); endfunction endclass module tst; class_1 c1[]; class_2 c2[]; c_base q[$]; initial begin c1=new[20]; c2=new[20]; foreach(c1[i]) begin c1[i]=class_1::type_id::create($sformatf("c1_%0d",i)); assert( c1[i].randomize() ); q.push_back(c1[i]); end foreach(c2[i]) begin c2[i]=class_2::type_id::create($sformatf("c2_%0d",i)); assert( c2[i].randomize() ); q.push_back(c2[i]); end q.sort with(item.index); $display("---------------"); $display(" Index Name "); $display("---------------"); for(int i=0; i<q.size();i++) begin $display(" x%h %s",q[i].index,q[i].get_name()); end end endmodule EdaPlayground link: https://www.edaplayground.com/x/3pk2 For the above code in EdaPlayground, I'm creating 20 objects for both classes and got same index value ( x398, x2d7) for a class_1 & class_2 objects. What I expected was, the index value of all objects will be unique until all combinations are exercised. My intention is to use "index" as the location of SRAM address to store the packed data of each extended class object. Is this the expected behavior in SimVision15.20?? Can't i get unique values for variable index ?
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Forum Post: RE: customizing ViVA result browser traces default settings
Update: Itwas working with the ".cdsenv" entry as well, but the testing I performed was misleading. When I start a new virtuoso session and the result browser opens automatically it opens with the Settings of the last sessions. I expected the result browser to open with the Settings given by .cdsenv. When the result browser is closed and openend again, then the Settings of the .cdsenv are applied. Problem solved, entries in ".cdsenv" are correct, testing was wrong !
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Forum Post: RE: Change Pins from VSS to DVDD and vice versa in the Schematic
Hi Utkarsh, rexReplace is a general pattern matching/replacement function - it takes a string as input and returns the updated string. It does not update any variable or expression. schReplaceProperty is explicitly for updating a named property on an object - it's not a matter of updating a variable, but it's designed specifically to modify a parameter on an object. So they do completely different things... Anyway, glad the updated code is working. Regards, Andrew.
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Forum Post: PCB 17.2 Step Mapping troubles
Hi i have some Troubles to map some 3D Step files. Here a view Samples. community.cadence.com/.../Step.zip Regards Peter
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Forum Post: RE: Feature Request: New 3D Engine PCB 17.2
Hi All. I am a liitle confused now. I have assumed that i receive some feedback after a i write to this Forum. Is this the wrong Methode ? I pay a lot off Money for the subscription and i allready a member within the Altium Beta Forum. This Forum typical answer my question. thanks. Peter
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Forum Post: RE: Feature Request: New 3D Engine PCB 17.2
This isn't the place for enhancement requests, you need to either file a case with cadence online support or with the channel partner you bought the software from.
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Forum Post: RE: PCB 17.2 Step Mapping troubles
So what's the problem here? The capacitor looks like it's lying down on the board with the holes off to the side. Mount the legs inside the holes with the body touching the surface of the PCB - or do you need a vertical version of the step model.
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Forum Post: RE: PCB 17.2 Step Mapping troubles
Hi Steve, than ks i follow your Information regarding the Support!. I can not map the Capacitor within the Step Maping Dialog. We have already try to reduce the step with a external tool "Freecad" but in General i can not map this capacitor. i send you a Screen shoot from a solidworks easm. thats explain the Situation. Thanks Peter
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Forum Post: RE: PCB 17.2 Step Mapping troubles
Can you attach the filename.dra you are trying to map the model to
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Forum Post: RE: same value for a RANDC variable of base class in extended class objects
It would help if you pasted the output that you're getting, as well as the actual code you're using. The code you pasted above doesn't compile. I modified it by moving the "module tst;" line to the top of the file and adding "include uvm_pkg::*;" and including the uvm_macros.svh file to get it to compile. I also had to change "rand" to "randc" for "index". What I see when I run it, is a list of unique IDs: --------------- Index Name --------------- x016 c2_11 x020 c1_0 x04e c1_10 x052 c1_12 x069 c1_9 x06d c2_2 x09b c1_17 x0a1 c1_1 x0a4 c2_8 x0ab c1_3 x0b2 c2_16 x0b5 c2_0 x0b8 c1_15 x0de c2_9 x0ed c2_10 x0f9 c2_14 x109 c2_19 x111 c1_4 x11a c2_13 x11e c1_2 x194 c1_11 x1be c2_6 x219 c1_18 x271 c2_1 x274 c1_6 x27e c1_14 x288 c2_7 x2e4 c2_15 x301 c2_3 x30a c2_17 x325 c2_18 x327 c1_19 x332 c1_5 x33c c2_4 x34a c2_5 x352 c2_12 x361 c1_7 x3c0 c1_16 x3cb c1_13 x3cc c1_8 Aside from that, I think perhaps you have a misunderstanding about how inheritance works. "index" is not a shared variable between class instances; there is one instance of "index" for every class instance. Thus if you have 2 instances of c1, there are two separate memory locations for "index", one for the first instance of c1 and one for the second instance. If both class instances start with the same seed, then they will both generate the same sequence of values for "index". If you want a truly unique "index" that isn't reused in any instance of c, c1 or c2, then make "index" a static variable so that the memory is shared between all the class instances. As a final point, "SimVision" is the GUI debugger, the simulator is called Incisive.
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Forum Post: RE: PCB 17.2 Step Mapping troubles
community.cadence.com/.../E_2D00_RM5X13_2D00_L21_5F00_AQUIS.zip
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Forum Post: fork (or run view() on different thread)
Is there a way to use the view() command in a different thread somehow? For example, in ADE-L, when a simulation is running, the spectre.out log window is getting updates but my virtuoso session is otherwise still responsive. I am guessing that this is because of using view() like view(my_file nil "my_title" t) and that spectre has been launched via ipc. Every once in a while I have something running in skill that is somewhat lengthy (10-20 minutes) and like to have an output log file get tailed. I tried view() but that window doesn't refresh until after the long job is done. In the mean time, I've been using something like: log_file="my_log.txt" log_port = outfile(log_file) fprintf(log_port, "Start of log...\n") drain(log_port) cid=ipcBeginProcess(strcat("xterm -sb -geometry 100x120+20+20 -title my_log -e tail -f " log_file)) ipcWaitForProcess(cid, 5) ;; long skill stuff that along the way writes to log_port close(log_port) ipcKill(cid) view(log_file) is this pretty much the only way or is there some way to tell view() to run in a different thread somehow? I'm guessing this is the only way but thought I'd ask and also since there is at least something that works, someone else may find it useful. This can be helpful in an ocean environment. -Dan
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Forum Post: Virtuoso ADE Explorer/Assembler problem with load balancing system (type SGE)
Dear All, I have come across problem when trying to run jobs over load balancing system of SGE type while using Virtuoso ADE Explorer and/or Assembler (IC_6.1.7.715 aka IC6.1.7-64b.500.15). I have no problems when it comes to older tools like ADE-XL. I had spent some time to debug it and by exploring inside of the farm node I have found out that : 1) if spectre job to be excuted is of single point (no parameter scans etc), then it does it on the farm node via axlGenerixGlobalLauncher script which calls runSimulation script - and all goes ok. 2) if job is of multipoints then as usual it uses runICRPxx script that launches nograph virtuoso which in normal conditions should start simulator via runSimulation script. However.. instead - it tries to launch simulator back on the submission host (!) via cdsRemshClient call. Here is the output of 'ps' command run over farm node farm036: [root@farm036 ~]# ps uaxwwf | grep user root 21420 0.0 0.0 9044 664 pts/0 S+ 17:34 0:00 \_ grep --color=auto user user 17608 0.0 0.0 22076 1712 ? Ss 17:31 0:00 \_ -sh /opt/sge/default/spool/farm036/job_scripts/42280 user 17649 0.0 0.0 9528 1344 ? S 17:31 0:00 \_ /bin/sh /projects/PDK/SigmaDelta/V1.0/workAreas/user/.tmp_user/.cmddir0/runICRP0 user 17688 3.7 0.7 1452752 467976 ? S 17:31 0:05 \_ /eda/cadence/2017-18/RHELx86/IC_6.1.7.715/tools.lnx86/dfII/bin/64bit/virtuoso -noautostart -mpssession virtuoso11005 -mpshost work053 -davinciService DaVinciService_11005_1519057891 -log /projects/PDK/SigmaDelta/V1.0/workAreas/user/logs_user/logs0/Job0.log -licenseLockFileName /projects/PDK/SigmaDelta/V1.0/workAreas/user/.tmp_user/.work053_11005 -nograph -nostdin -axlChildIdFlag 0 user 21410 0.0 0.0 2460 708 ? S 17:34 0:00 \_ /eda/cadence/2017-18/RHELx86/IC_6.1.7.715/tools/bin/32bit/cdsRemshClient work053 -cdsPath tools/bin/cdsServIpc -s farm036 -c 47686 -n 1 -r 0 -x cd /simulation/user/ResDir/testWB/testInverterTB/maestro/results/maestro/ExplorerRun.0/1/testWB:testInverterTB:1/netlist ; ./runSimulation user 21418 0.0 0.0 0 0 ? Z 17:34 0:00 \_ [cdsRemote.scr] where work053 is the submission host (where main ADE Explorer is run) and farm036 is the farm node. so far I have cut .cdsinit init to the minimum and tried: ;; forcing distributed mode to NOT copy files into exec machine: envSetVal("asimenv.distributed" "copyMode" 'boolean nil) ;; disabling interactive ADE Assembler and Explorer modes: envSetVal("maestro.simulation" "interactiveE" 'boolean nil) envSetVal("maestro.simulation" "interactiveA" 'boolean nil) ;; forcing to use ssh in remote shell calls: envSetVal("asimenv.distributed" "remoteShell" 'string "ssh") ;; helpers for debugging ADE-XL/Assebler : (when (axlIsICRPProcess) _axlDebugTimeFlag = t (sstatus errsetTrace t) _stacktrace = 50 ;_axlCallbkDebugFlag = t ;uncomment this if debugging callbacks ) ;; make stdout and stderr visible (envSetVal "adexl.icrpStartup" "showJobStdout" 'boolean t) (envSetVal "adexl.icrpStartup" "showJobStderr" 'boolean t) and set env. variable AXL_PEJM_DEBUG=3 as suggested in one of trouble shutting articles on the KB. As I had mentioned above - I have no problem with job executions over SGE farm while using ADE-XL tool. Any ideas ? Wojciech
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Forum Post: RE: PCB 17.2 Step Mapping troubles
I don't think the orientation of your footprint can match the step model you have, try rotating it by 180 and then see if that helps. I've attached a zip file with your dra file plus a couple of screenshots - although I did this in 17.2 so you will need to repeat the settings for your 16.6 version. community.cadence.com/.../fixed.zip
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