Thanks to point this out. It was in the examples of Doulos not very clear. The driver works when instantiated in env or test class. I know this is the not the best. I will take a look at UVC agents from now on.for better and proper UVM test structure.
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Forum Post: RE: run_phase doesn't update SV interface signals
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Forum Post: Error running Liberate_AMS
I'm getting the above shown error when running Liberate_AMS . I dont have any instances 'bsource' or 'cab' in my netlist..Can anyone help what that error refers to ?
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Forum Post: RE: To get resistance of track
OK try a new report file that contains this:- GEOMETRY # Select: CLASS = ETCH # Data fields to be written out: CLASS SUBCLASS NET_NAME = THE ACTUAL netname SEG_CAPACITANCE SEG_INDUCTANCE SEG_RESISTANCE GRAPHIC_DATA_1 GRAPHIC_DATA_2 GRAPHIC_DATA_3 GRAPHIC_DATA_4 GRAPHIC_DATA_5 GRAPHIC_DATA_10 # End of Command File END You can save this as a .txt file and edit it in a text editor so put the actual netname, once that's there save it in the same directory as your board file and then it will be available in the Tools - Reports list at the top (scroll down to see your report text name).
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Forum Post: RE: Is there a way to describe the charge across the device as a function of voltage?
Like I said before, I get "error" displayed when I try to upload a file (even though its within the permissible size limit and the file name is withing the permissible number of characters).
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Forum Post: RE: Is there a way to describe the charge across the device as a function of voltage?
Sorry, I didn't see that in your earlier post. Can you try a different browser (not sure which you're using)? Also, how big is the file? If it's not that big, could you just paste the contents into the post? It's just a text file after all... Andrew.
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Forum Post: RE: Is there a way to describe the charge across the device as a function of voltage?
It crashed my browser when I tried c&p. The file is ~400 kb which should be withing the limit (750 kb). I tried a different browser and it still failed. I uploaded it to the link below. https://files.fm/u/9q2e4xua
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Forum Post: How can you change the waveform viewer defaults to thicker lines and not dotted?
I've looked over a couple previously posted solutions, e.g.: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/34307/default-colors-in-waveform-viewer However I can't seem to make this work. I've tried opening the Display Resource Editor and tweaking y0-y9 without success. I continue to see waveforms as shown in the picture. Any ideas?
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Forum Post: RE: How can you change the waveform viewer defaults to thicker lines and not dotted?
Sigh - I spent a while looking for a solution, gave up and then made this post. Then I looked a little more and found the answer 5 minutes later :-/. Here it is: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/15018/the-defalut-line-type-in-wavescan/26465#26465 In particular, I need to add the following to my .cdsinit: envSetVal("wavescan.trace" "lineStyle" 'string "solid")
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Forum Post: RE: How can you change the waveform viewer defaults to thicker lines and not dotted?
The line style for y0-y9 affects signals (sent from outputs in ADE) so that they cross-probe on the schematic with the same colour and style; for waveforms plotted by other ways, it uses the ViVA default that you found. Regards, Andrew.
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Forum Post: RE: How can you change the waveform viewer defaults to thicker lines and not dotted?
Thanks (as always) Andrew.
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Forum Post: RE: detecting process corner from within verilogA model
Thank you, I am following this thread because I need to implement the same and I have a question. I have created a file called "wrapper.scs" which looks exaclty like this: library wrapper section NN parameters corner=1 include "gpdk.scs" section=NN endsection NN section FF parameters corner=2 include "gpdk.scs" section=FF endsection FF endlibrary wrapper In ADE-L I select Setup/Model-Libraries/ then I select the path to the model file "wrapper.scs" and I can select between the two sections "NN" and "FF" (the original file gpdk.scs has more sections). So this part is working fine. My question is how to read the value of the parameter "corner" into the veriloga model. I am lost here. Thank you very much!
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Forum Post: RE: Error running Liberate_AMS
There is a work round for this. Look through your models and look for subckt that has a line of "cab ( ) bsource" or higher level model that calls for such subckt. Add it to leaf cell, type can be blackbox if the model is not used in the netlist. I suggest you submit a support Case with your test case. So that our R&D team may implement an enhancement.
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Forum Post: Cascaded display.drf loading
I have an on-going battle with Virtuoso trying to make things work and/or not look disgusting with everything on a white background (so I can always have WYSIWYG when I print stuff). I made my own display.drf file that contains (so far) only the things I need to make schematics look good on a white background. My most recent hurdle was figuring out what defined the color of selected items like wires or labels etc. Before I fixed it, that color was white (which annoyingly makes the selected items invisible on a white background). For the technology I'm using, the solution proved to be the following line in my display.drf file: ; color of selected items (lpp = align/drawing). ( display defaultPacket blank dashed red red outline ) However, I've since found as I bring more tools into the fold that I need to prevent my display.drf file from loading first because (for reasons unknown to me) it appears to block other display.drf files from other libraries loading. To get around that I added the following to my .cdsinit: ; Force Cadence to load the tsmc18 library and read it's display.drf file first ddGetObj("tsmc18")~>techLibName ; Now superimpose my display.drf file on top of it ; The nil means it won't ask you to save it when you quit Virtuoso drLoadDrf("./display.drf" nil) After I do the above, everything in my schematics continues to look as per my display.drf *except* for the color of the selected items as outlined above - they're coming out as white again :-(. I'm guessing maybe another rogue display.drf file is being loaded after mine, but darned if I know to determine or fix that. Any ideas? Note that I realize I could just let everything load up, go into the Display Resource Editor and then merge my display.drf file into it and save the result (assuming "merge" means anything set in my file overrides existing stuff). However, that would become a maintenance nightmare after a while as I move from project to project.
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Forum Post: RE: Cascaded display.drf loading
More info: I should add that if I go into the Display Resource Editor I can still confirm that align/drawing is still set to red i.e. it doesn't seem to be overwritten. Now I'm really not sure what's going on.
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Forum Post: RE: How can you change the waveform viewer defaults to thicker lines and not dotted?
Sigh - I thought I had this all locked down, but now that I've gotten out and then back into Virtuoso I'm right back where I started i.e. a waveform viewer with thin dotted lines. I've tried editing y0-y9 again without luck, and when I try envSetVal("wavescan.trace" "lineStyle" 'string "solid") that doesn't do anything either. I'm so confused. Would somebody mind please providing a bullet-proof set of instructions to make this work robustly. Thanks.
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Forum Post: RE: Is there a way to describe the charge across the device as a function of voltage?
You still didn't say which version of spectre you were using. BTW, I was able to upload the file OK when I tried to... Anyway, I think the issue is that the ddt doesn't know the tolerances of the polarisation variable - I got it to work by doing: electrical internal; V(internal) <+ polarization; I(p,n) <+ ddt(V(internal))*0.00000000001135; I then also needed (in MMSIM13.1 or later) to do: setenv CDS_AHDL_CONVERT_INTERNAL_NODES NO before running the simulation (starting virtuoso/icfb) Andrew.
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Forum Post: VIVA Table SKILL functions
Hello: I was looking for SKILL functions to work with VIVA tables and so far I have found only a single function. awvTableSignals However this function is very limited. Are there any other functions available for working with VIVA tables? Specifically I was looking for functions to perform the following basic tasks: Open a new, blank VIVA table and possibly return some identifier or object instance of it. Add a waveform object to a table as a column in that table. The awvTableSignals function requires a strange "l_siglist" list to identify the contents and only accept signal names as strings. -Curtis
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Forum Post: axlShell does not work
Hi guys, i and trying to add variable in axlshell() but it does not work. anyone can help? This is my code layer = "DRILL" sprintf(s "FORM vf_vis colorview_list Film:%s" layer) axlShell(s) Error msg: E- Value for field is not legal =( Regards, Eugene
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Forum Post: Bindkey for raising CIW problem
Hello, First of all, I am quite new to programming in SKILL. I've tried to raise the CIW window by using a bindkey F3 by using this code: procedure(raiseCommandInterpreter() applicationList = list("Schematics" "Layout" "Artist" "adexl") foreach(application applicationList hiSetBindKey(application " F3" "hiRaiseWindow(window(1))") printf("Bindkey set for raising CIW window for %s. \n" application) ) ) The bindkey works in schematic and layout, however, in ADE(X)L is does not raise the window... Is there something I missed? Kind regards, Nicolas
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Forum Post: RE: VIVA Table SKILL functions
Curtis, No, unfortunately not. Regards, Andrew
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