You can add the variant name to the title block. If you add a property called Variant Name (with the space), when you select that BOM variant, the name given to the variant is populated.
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Forum Post: RE: Capture CIS Variants - Custom titleblock properties
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Forum Post: RE: Capture CIS Variants - Custom titleblock properties
As stated in the original question, the functionality you refer to has been there for over 2 years. I was requesting the ability to tie multiple other properties (e.g., document number and assembly number) to the variant name and have them displayed, not just the variant name.
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Forum Post: RE: Capture CIS Variants - Custom titleblock properties
My hack was to use the Variant Name as the document number, making the title generic. You still only get one variable for Variant View Mode, so it doesn't solve much. I still had to edit the titleblocks manually if I wanted to change the revision for example.
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Forum Post: how to open a .brd file in capture
Hi all Is there a direct way to open .brd file in capture or i need to export it as something else? I'm using 17.2 Regards Z.
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Forum Post: Using Skill for Naming Large Numbers of Pins
Hello, I am interested in learning how I could write a SKILL script to create a large numbers of pins to be used in a 1 KB 6t SRAM chip. These pins would then need to be individually named and connected to the correct instance pins. I currently have a single SRAM cell (schematic, layout, DRC and LVS completed), but expanding this to 1 KB has proven a challenge because I do not know how to create, connect, and correctly name the very large number of pins that would be necessary. Is there a way to automate this process using SKILL? Thank you
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Forum Post: how to append a constraint with cstCreateConstraint
Hi, I want to append a constraint "minOppExtension" in my techfile. So I'm using cstCreateConstraint to do it. techID = techGetTechFile(ddGetObj("Tech")) cutClass_CG=cstFindConstraintGroupIn(techID "group1") cstCreateConstraint(cutClass_CG "minOppExtension" list("M2" "V1") list(0.0 0.0) list('cutClass list(0.04 0.04)) t t) it return nil What is wrong with my code it should be like that in the techfile constraintGroups( ;( group [override] [definition] [operator] ) ;( ----- ---------- ------------ ---------- ) ( "group1" nil nil 'and orderedSpacings( ( minOppExtension "M2" "V1" 'cutClass (0.04 0.04) (0.0 0.0)) ) ;orderedSpacings ) ;group1 ) ;constraintGroups Thanks
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Forum Post: Disable v17.2 Start Page
Hi, I just updated from OrCAD PCB Editor v17.2 S001 to v17.2 S038. According to the documentation, the new Start Page was added in S031. How can I turn this off? I know how to do it in Capture, but can't find out how to do it in PCB Editor. Thanks. --Mark
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Forum Post: RE: Verilog A to symbol
I don't see why you think you need to `include one module in another. Why are you doing that? Regards, Andrew.
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Forum Post: RE: Skill command to delete label from layout
There was a bit of code posted earlier (which seems to have been removed), and I was going to suggest an improvement to it to avoid creating some unnecessary list cells (the original code had a foreach on the result fo a setof). You can just do: cv=geGetEditCellView() when(cv->cellViewType=="maskLayout" foreach(shape cv->shapes when(shape->objType=="label" dbDeleteObject(shape) ) ) ) Regards, Andrew.
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Forum Post: RE: Verilog A to symbol
Because each file contains electrical representation of effects such as schottky, transistor resistance etc, b1 contains core model, b2 contains various effects and b3 is the top level definition of the device. Regards Shobhit
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Forum Post: RE: Verilog A to symbol
Hi Shobhit, If you have three modules - b1, b2, and b3, and b3 instantiates b1 and b2, there is no need to `include the other files to use them. The spectre netlister will see the hierarchy and make sure all three files are included (via ahdl_include) into the spectre netlist. Of course, given that you've not shown the code, I'm reliant on guesswork, but given the symptoms you've described it sounds possible that you've done that. If you want a more precise answer, please post the code you're using so we don't have to guess. You've also not stated any tools, versions or anything like that. Please read the forum guidelines - we all do this in our spare time, and so it's rather frustrating having to go backwards and forwards trying to collect information to clarify the question. Kindest Regards, Andrew.
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Forum Post: RE: Verilog A to symbol
Kindly forgive me for the negligence. Im using IC 5.1.41 and please find the code below:- `include "disciplines.vams" `include "PCNFET_L2.va" module PCNFET(Drain,Gate,Source,Sub); // Input variables definitions parameter real Lch=`L_channel; parameter real Lgeff = `Lceff; parameter real Lss=`L_sd; parameter real Ldd=`L_sd; parameter real Efi=`Efo; parameter real Kgate=`Kox; parameter real Tox=4.0e-9; parameter real Csub=20.0e-12; parameter real Ccsd=`Ccsd; parameter real CoupleRatio=`CoupleRatio; parameter real Vfbp=0.0; parameter real Dout=1.0; parameter real Sout=0.0; parameter real Pitch=20.0e-9; parameter real Wgate=`sub_pitch; parameter real CNTPos=1.0; //not used parameter real n1=19; parameter real n2=0; parameter real tubes=1.0; // Electrical connections inout Drain, Gate, Source, Sub; electrical Drain, Gate, Source, Sub; electrical int_Drain1, int_Gate1, int_Source1; //For XPCNFET_L2_edge with CNTPos=1 electrical int_Drain0, int_Gate0, int_Source0; //FOR XPCNFET_L2_midd with CNTPos=0 real Cgpar; //HSPICE uses the 'm' parameter. //Here, probes are used along with CCCS to multiply all currents. //Model edge tubes: probe the currents going into 1 instance branch (Drain, int_Drain1) probe_drain1; branch (Gate, int_Gate1) probe_gate1; branch (Source, int_Source1) probe_source1; PCNFET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbp(Vfbp),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(1),.n1(n1),.n2(n2)) XPCNFET_L2_edge (int_Drain1, int_Gate1, int_Source1, Sub, int_Drain1); //Model the middle tubes: probe the currents going into 1 instance branch (Drain, int_Drain0) probe_drain0; branch (Gate, int_Gate0) probe_gate0; branch (Source, int_Source0) probe_source0; PCNFET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbp(Vfbp),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(0),.n1(n1),.n2(n2)) XPCNFET_L2_midd (int_Drain0, int_Gate0, int_Source0, Sub, int_Drain0); analog begin begin // Assign basic parameter Cgpar = `Ctot*Wgate; end //model the other (min(tubes,2)-1) edge tubes with CC-CS I(Drain, Sub) <+ (min(tubes,2)-1)*I(probe_drain1); I(Gate, Sub) <+ (min(tubes,2)-1)*I(probe_gate1); I(Source, Sub) <+ (min(tubes,2)-1)*I(probe_source1); //By KCL, the current on node Sub is also scaled automatically //model the other (max(tubes-2,0)-1) middle tubes with CC-CS: I(Drain, Sub) <+ (max(tubes-2,0)-1)*I(probe_drain0); I(Gate, Sub) <+ (max(tubes-2,0)-1)*I(probe_gate0); I(Source, Sub) <+ (max(tubes-2,0)-1)*I(probe_source0); //By KCL, the current on node Sub is also scaled automatically // Placing component // Capacitors I(Gate,Sub) <+ ddt(Cgpar*V(Gate,Sub)); end // End: analog begin endmodule thank you for your time and patience Andrew Regards Shobhit Referred from:- nano.stanford.edu/stanford-cnfet-model-verilog
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Forum Post: RE: single layer pcb
I'm having the same issue as this. Was a solution ever found?
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Forum Post: RE: Unable to map design without a suitable latch. [MAP-3] [synthesize]
Thanks for sharing this information. I really like your blog post very much. You have really shared a informative and interesting blog post . Magnesium
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Forum Post: RE: How to remove/ delete the pre-existing home path and point it to new location
Hi, there is just not enough information to determine how you did the install. When you launch capture do you receive an error, is the PCB editor working, what about the licensing is that also installed on your D drive or somewhere else. When you installed the software did you install it for all users ? or the current user ? I think it is best to uninstall everything then re-boot. Before you install again remove the env variable in the system properties if it is still there. It probably will be. Paul.
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Forum Post: RE: How to remove/ delete the pre-existing home path and point it to new location
Hi, I have followed the normal procedure for installation. When I launch the capture it opens but the home path displayed on start page is pointing to earlier home path at C drive. The installation is for all users and licensing is done on D drive. Thanks, Shivaprakashh
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Forum Post: RE: Disable v17.2 Start Page
Setup - User Preferences - Ui - Startpage - and check allegro_no_startpage then restart
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Forum Post: RE: how to open a .brd file in capture
No but you can use PCB Editor or PCB Editor Lite if you don't have a licensed version. There is also an allegro_free_viewer.exe located in the installation folder
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Forum Post: How to use tabs in the new Allegro GUI?
Dear All, the new GUI of Allegro gives the possibility to use tabs to open multiple layouts. How to use it? Also, how many licenses are used? one per layout? Thanks Francesco
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Forum Post: RE: How to use tabs in the new Allegro GUI?
At the moment you can't. It's there for the new Start Page and the design you have open. Maybe in a future ISR/QIR this may change but only Cadence knows.......
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