Glad it worked. Here's how I connected up my test bench - you can specify the bus syntax slightly differently: Regards, Andrew.
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Forum Post: RE: Changing the number of input bits in a DAC and problem in ADE simulation
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Forum Post: Difference between V(P1,T1)
Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in Verilog A I think V(P1, T1) <+ 0; would mean voltage difference between node P1 and node T1 is 0 and V(P1) <+ V(T1) would mean potential difference between P1 to gnd is equal to T1 to gnd. I feel these statements kind of means the same, but when I used these statements in 'if block' in 'Verilog A', use of each statement gives different results, can someone please explain what difference does it make between these statements. Also, can we use these statements in an 'if block'?
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Forum Post: RE: Unable to import psm path
Sorry for the late responce I tried putting everything flat and it wasn't successful. I tried placing some resistors too and it was showing errors with it and this time the error was E- because WARNING(SPMHUT-127): Could not find padstack S_00508X00508R05_1. With Padstack: ERROR(SPMHDB-181): Design revision 15.x is too old. Must run the batch dbdoctor to uprev. So I checked the pad stack I was pointing to and ran DBDoctor "You have to go to the Start>Programs>cadence SPB 16.2> PCB Editor Utilities>DB Doctor select the board or library files and run update." mashak from post https://www.edaboard.com/showthread.php?127597-Allegro-PCB-Editor-and-OrCAD-PCB-Editor I will update it. It looks like it might take a few days.
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Forum Post: ade explorer set instance value
hi, i create one simulation in ade assembler, several test for simulation, for example, i place one analoglib “port” in schematic, but different test need to set different port source type, like dc and sine, how could i to switch cross different test in ade explorer? for PAC simulation, i need to check display small signal params and set PAC level( iknow ican set variable for this level), how can i to control check box? if checkbox is not cheched, and i set PAC level by variable, is this variable take effect? thanks
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Forum Post: RE: Difference between V(P1,T1)
They're not identical - because the first is like having a zero-volt source between the two nets, and the second is like a voltage-controlled voltage source. So that means that in the first case current flows between P1 and T1, but it doesn't in the second case. You should never (well, almost never) put contribution statements within an if statement (the "almost" case is when you have a switch branch which switches from a voltage source to a current source - usually to model a switch opening or closing). Otherwise you end up with a contribution that isn't active all the time, and the node (or branch) ends up uncontrolled for some of the time, which presents a problem for the matrix solver, as it means you have an ill-conditioned matrix to solve. Regards, Andrew.
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Forum Post: RE: ade explorer set instance value
Well, one way to do this is to have a port (or vsource or isource if that's appropriate - you don't have to use "port" for RF simulations), and set it to sine all the time. Then specify the frequency as a variable and then if that variable is set to 0 for that test, then it is a DC source. If it's non-zero, then it's a sinusoidal source. It's perfectly OK to set the PAC magnitude even when you're not using PAC analysis. The "display small signal params" doesn't affect simulation in any way (same is true of the other "display" parameters); it just controls whether the fields are shown on the edit properties/create instance form. So you can fill in the PAC magnitude and then turn off display, and it will still use them (I wouldn't recommend this though, because it's confusing to a reader of the schematic because they can't see the hidden parameter). Regards, Andrew.
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Forum Post: RE: Assura LVS for Standard Cell Library with only Abstract View
hi Daihyun Would you please try adding ?blackBoxCell avParameter cmd to see if it helps? By the way, this thread has already ended more than 4 years ago. It would be best if you can start a new thread for your issue. This will help us to focus on only your issue and not be confused by old comments. Best regards Quek
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Forum Post: RE: Difference between V(P1,T1)
thank you for your explanation. I am trying to simulate a switch and when I used these statements in an 'if block', I get 'zero diagonal and jacobian' errors. Could you please suggest the best choice if I am simulating an switch
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Forum Post: how to generate spectre netlist for all the schematics in 1 lib ?
Hi , I would like to generate spectre netlists for all of the schematic cell in my lib. What can I do ? I search in the forum but didn't the answer yet thanks Nhumai
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Forum Post: RE: Difference between V(P1,T1)
If you want an explanation as to why your model misbehaves, it's generally best to actually show your model. My extra-sensory-veriloga-perception isn't working too well at the moment (I blame jet lag), so I can't guess what you've done. For some examples of switch models, see http://www.designers-guide.org/VerilogAMS/ Regards, Andrew.
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Forum Post: RE: how to generate spectre netlist for all the schematics in 1 lib ?
Hi Nhumai, Something like the following (untested) code: simulator('spectre) lib=ddGetObj("libName") foreach(cell lib~>cells when(ddGetObj(lib~>name cell~>name "schematic") design(lib~>name cell~>name "schematic" "r") createNetlist(?display nil) ) ) Regards, Andrew.
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Forum Post: PCB Editor: possible to adjust embedded net names "density"?
Hello! I'd like to increase the "density" of the net names in PCB Editor, as sometimes (specially in close zoomed-in views) large shape areas don't display a label, and one needs to "zoom-out" to catch one of the net names displayed. Is this tweakable somehow? Thanks and regards, Jorge.
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Forum Post: RE: how to generate spectre netlist for all the schematics in 1 lib ?
Hi Andrew, I am new to skill script please help to let me know how to use it ? thanks Nhumai
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Forum Post: RE: how to generate spectre netlist for all the schematics in 1 lib ?
Hi Nhumai, Either take the code above (with the correct library name where it has "libName") and paste it in the Command Interpreter Window (CIW), or probably better to put in a file, save the file, and then in the CIW type: load("theScript.il") (where "theScript.il" is whatever you've called the file). Regards, Andrew.
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Forum Post: How do I nc_mirror two enum from VHDL to verilog?
I am trying to nc_mirror some signals from VHDL DUT (non-modifiable) to my SV testbench. There are two VHDL enum state machines which use IDLE. However SV doesnt seem to accept two enums sharing the same element IDLE. What may I do in my testbench to get arround this issue? module tb_probe_abcd; typedef enum integer {IDLE, ST_A, ST_B} t_ab_state; t_ab_state ab_state; typedef enum integer {IDLE, ST_C, ST_D, ST_E } t_cde_state; t_cde_state cde_state; initial begin $nc_mirror("ab_state", "sv_top.dut_wrapper:VHDL_DUT:ab_state"); $nc_mirror("cde_state", "sv_top.dut_wrapper:VHDL_DUT:cde_state"); end endmodule : tb_probe_abcd
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Forum Post: RE: Help with exporting .ART with SKILL
I played around and found 1 option that finally worked for me films = axlGetParam("artwork")->groupMembers filmLayers = rexMatchList("^[0-9][0-9][0-9][0-9][0-9]-[0-9]_[A-Z][0-9][0-9]$", films) foreach(films1 filmLayers axlRunBatchDBProgram("artwork" strcat("artwork -f " sprintf(films1 " %s " films1) axlCurrentDesign(), ".brd"), ?noUnload t ?logfile "photoplot.log", ?warnProgram t)) i added sprintf inside the strcat. dont know if its a good practice to do that. now axlRunBatchDBProgram run through whatever films i need to export (fingers crosses)
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Forum Post: RE: Unable to import psm path
You can use wildcards in dbdoctor so try browsing for a padstack (filename.pad) then edit it to say \*.pad which will do this as a batch on all padstacks. Repeat for *.dra. That should seed things up.
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Forum Post: RE: NC-Verilog user manual
Hi Stephen, I registered for the support, thank you for this information. Also the trick with the "decompile " in ncsim, worked like a charm. I used the following command: ncdc -output ./mydc.v my_lib.top:snap and it did the job by bringing in-line all the "included" modules. Always helpful with your answers, thank you! Kind regards, anm
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Forum Post: RE: Replace "`includes" with in-line modules - NC-Verilog
I managed to found the solution. In ncsim environment, after the compilation of the top Verilog netlist, I run the command ncdc -output ./mydc.v my_lib.top:snap and it generated a top Verilog file with all the "included" modules now inline. I am posting my answer in case someone finds it useful.
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Forum Post: RE: NC-Verilog user manual
Great! I'm glad it worked for you, thanks for the update.
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