Hi Andrew, Your reply cleared the confusion. I thought this function will be triggered for events like some object is selected or some object is created/modified/moved/deleted. Is there any function to do the above in layout/schematic/symbol? -Ramakrishnan
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Forum Post: RE: hiRegCurWindowTrigger usage
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Forum Post: RE: hiRegCurWindowTrigger usage
There is for selection in layout - use leRegUserObjectSelectionFilter. However, the answer is "no" for the other operations in layout, and no for any of the operations in schematic or symbol. Andrew.
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Forum Post: RE: hiRegCurWindowTrigger usage
Ok. Thanks for the information. Looks like such API is not available for public. But how do some third party tools like Calibre Real Time is capable doing such (post edit) things. I can understand the ability of DRD/iPVS to do so. If this comes under some NDA you can say so. I can understand. -Ramakrishnan
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Forum Post: Unbound pins after LVS of a Innovus implemented instance
Hello all, I've implemented a digital block in Innovus and I need to simulate it in an analog environment with AMS, so I imported the layout in Virtuoso (6.1.7) to get the analog_extracted view. I also imported the verilog netlist and converted it into a schematic via File->Import->Verilog on Virtuoso, to perform the LVS with Assura. However, although I got no warnings or errors from Innovus, when I try to perform the LVS there are two unbound pins, vdd! and gnd!. Consequently, I also can't get the analog extracted view vith Quantus QRC because it can't find the gnd! net (seems like it doesn't exist), with the following error: ERROR (FINDCAP-88016): cap ground signal 'gnd!' cannot be found.ERROR (FINDCAP-88016): cap ground signal 'gnd!' cannot be found.Check if net 'gnd!' exists in design and has the correct ?netNameSpace (schematic, layout) specified in RSF. On Virtuoso Layout XL I can correctly see the names of the vdd! and gnd! nets, and also the connectivity of the metal paths that make the power ring seems ok, so thinking that the pins were simply missing I tried to create labels and then perform the command Tools->Create pins from labels, but the resulting created objects seem to be of type "Shape" instead of type "Pin" and are still not found during LVS. I still don't know if the problem is during the Innovus flow or maybe there are some missing steps in the transition between Innovus and Virtuoso. Any help or ideas are appreciated, Thanks Stefano
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Forum Post: RE: problem with resistor in corner analysis
My problem has been resolved i added ff_res to my corner . i did that before and it It did not work at that time but it works now i don't know what happened thank you for your time
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Forum Post: RE: PCB Editor: how to transfer layer color setup between boards?
Jorge, I have been using 16.6 based upon my customer requirements, however this morning I switched to 17.2 & tested the 'export parameters' output, the output file doesn't appear to contain the design data you refer to as "Class/Subclass (user selected)" layers.
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Forum Post: RE: Virtuoso L and virtuoso xl cost ?
Hi Andrew, Thank you very much for the info. Best regards, Marben
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Forum Post: RE: Capture Symbol Property Configuartion
You can do it using TCL code.
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Forum Post: RE: hiRegCurWindowTrigger usage
Hi Ramakrishnan, No, this is not available even under NDA. I cannot comment about what any third party might be doing. Regards, Andrew.
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Forum Post: RE: PCB Editor: how to transfer layer color setup between boards?
Oh, I see. Then they must have changed this in v17.2. If you find a way to achieve the export/import of the "Class/Subclass (user selected) " layers in v17.2, please let me know!. Thanks and regards, Jorge.
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Forum Post: Is there a way to change the value of a voltage source (or a generic parameter), "during" the execution of an Interactive mode AMS simulation?
Hello all, I was wondering if there is a way to change the value of a voltage source interactively, during the execution of an AMS simulation. In SimVision, I can not deposit a value on a VerilogA model parameter, like DC value or delay. An example would be how to create the following waverform with user commands: . Any help or idea will be very much appreciated. Many thanks in advance and best regards, Ardit
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Forum Post: about lines startend points
i want get all lines start and end points on outline layer, there is the code defun( apl () let( (RLP symbPg symbPth allSymbols allSymbolss) ;print all lines startend point axlSetFindFilter(?enabled list("noall" "lines") ?onButtons list("noall" "lines")) allSymbols = axlGetSelSet(axlAddSelectAll()) axlClearSelSet() foreach( everyLine allSymbols axlMsgPut("startis %L" everyLine->startEnd) ; it doesnt work ;axlMsgPut("startis %L" everyLine->?) ;checked it has startEnd properties ;axlMsgPut("startis %L" everyLine->??) ;checked it has startEnd properties ) )) what's the right way ? and in the skill UG there is a starEnd attribute as in image below. how could i do it ?
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Forum Post: How to use rand_bit_stream for trasimpedance amplifier ?
hi i need to simulate eye diagram with cadence 6.14 for my transimpedance amplifier .transimpedance amplifiers input is current. i know i should use rand_bit_stream from ahdllib for generating random bits but its a voltage source and i need current source i saw that someone said Use VCCS but i dont know how to use rand_bit_stream with vccs because rand steam has 1 output but vccs has 2 inputs . another thing is how to make 2^31-1 bits i thought it means that we should do a transient simulation for 32767*period is that it?
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Forum Post: RE: X-out on assembly variants
I did and still it is not exactly what I am looking for, there is issue with rotated components. I have idea how to solve it but I am not able to find out how to get coordinates of corners for shape from "PACKAGE GEOMETRY/DFA_BOUND_(TOP,BOTTOM)" Could you please help with that. One more: how to display dbid attributes ? I try to do but without success: axlClearSelSet() axlSetFindFilter(?enabled '(components) ?onButtons '(components)) result=axlGetSelSet(axlSingleSelectName("COMPONENT" strcat("U10000"))) printf("Result: %L\n", result->??)
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Forum Post: ADE XL setup not working properly.
Hi. I use IC6.1.7 - I've just setup the software, via installscape, and using my institutions license server. All of that is working. I have a simple schematic that works fine simulating in ADE L , using a DC analysis. I am not using a config view. I launch ADE-XL , the working tests from ADE-L are imported. However I cannot plot any results, like used to work in ADE-L. I get the following messages (in red) in the CDS.log viewer, when I first launch the ADE-XL. *Error* Cannot copy "" from "/home/andy/cadence/installs/IC617/sims/comparator_tb/spectre/schematic/netlist" to "/home/andy/cadence/installs/IC617/sims/stochasticADC/comparator_tb/adexl/results/data/.tmpADEDir_andy/stochasticADC:comparator_tb:1/stochasticADC_comparator_tb_schematic_spectre/netlist", cpDataDir call returned 0 >> (... in _axlTarCopyWrapper ...) (... in unknown ...) (... in _axlImportADELTestInADEXL ...) (... in unknown ...) (... in _axlImportTestInADEXL ...) _axlImportTestInADEXL('sevSession25 ?appName "ADE XL" ?tool "ADE") Then when trying a single simulation run in ADE-XL I get: *Error* Error during netlisting of design for the point ID (0 1). ("error" 1 t nil ("*Error* Cannot copy \"netlist into run netlist\" from \"/home/andy/cadence/installs/IC617/sims/stochasticADC/comparator_tb/adexl/results/data/Interactive.0/1/stochasticADC:comparator_tb:1/netlist\" to \"/home/andy/cadence/installs/IC617/sims/stochasticADC/comparator_tb/adexl/results/data/Interactive.0/psf/stochasticADC:comparator_tb:1/netlist\", cpDataDir call returned 0")) ERROR (ADEXL-5025): Preparation to run the simulation is failed for the run Interactive.0, point 1, test stochasticADC:comparator_tb:1, received error: Error: ------------------------------ Error while preparing to run the simulation. Cannot copy "netlist into run netlist" from "/home/andy/cadence/installs/IC617/sims/stochasticADC/comparator_tb/adexl/results/data/Interactive.0/1/stochasticADC:comparator_tb:1/netlist" to "/home/andy/cadence/installs/IC617/sims/stochasticADC/comparator_tb/adexl/results/data/Interactive.0/psf/stochasticADC:comparator_tb:1/netlist", cpDataDir call returned 0 For details open log: /home/andy/CDS.log for the point: (0 1) ------------------------------
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Forum Post: RE: How to use rand_bit_stream for trasimpedance amplifier ?
Well, the vccs has a differential input, so if you've just got a single-ended input like the output from rand_bit_stream, then connect the negative input terminal of vccs to ground (gnd!). I don't know what you mean by making 2^31-1 bits. You should ask whoever is asking you to do this - it doesn't make a great deal of sense (and BTW, 32767 is 2^15-1, if that's even relevant). Regards, Andrew.
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Forum Post: RE: ADE XL setup not working properly.
This looks like the problem in article 20130330 . Most likely you've put $CDSHOME/bin in your path only, and so it can't find the cpDataDir script in the installation. Currently there's a requirement that you (also) have $CDSHOME/tools/dfII/bin in your UNIX path too. When I didn't have tools/dfII/bin in my path, I see this error, as well as getting: sh: cpDataDir: command not found appearing in the terminal window several times. Can you try that? Regards, Andrew.
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Forum Post: RE: Inconsistency in maestro result DB using SKILL
Hello Andrew, Is there a known workaround for this issue in version 1 2.3-64b.500.20? Best regards, Karam
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Forum Post: RE: Create a symbol from layout
This is a bit of an open-ended question, especially as you didn't say which tools you're using. Which LVS tool are you using? I wouldn't expect that you'd get an error saying that a symbol couldn't be read though. Broadly speaking I'd expect that you have to: Create the symbol with the right pins Copy this across to the auCdl view (or auLvs view - depends on which tool you're using for LVS) In the CDF, ensure that the component will be netlisted correctly to match your LVS extraction rules In the LVS deck, you'll have to add logic to recognise the device - i.e. some kind of recognition layer to identify the device correctly and figure out the connectivity to the pins. Maybe some parameter extraction to work out whether the dimensions of the transformer match the schematic, if you're not going to treat it as a black box. Alternatively, you might just create a schematic for the transformer with metal resistors at each pin to stop the pins from being seen as shorts (since the transformer coils are just metal tracks between pins), and then add those metal resistors on the transformer layout. It's not really checking that the transformer is present in the LVS, but at least you can manually check the transformer and allow a component in the schematic for simulation without it getting in the way of LVS. If this is unclear, contacting customer support would be a good idea. Trying to explain all this (briefly) in a public forum with such little information to go on is quite hard! Regards, Andrew.
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Forum Post: RE: ADE XL new test addition on a running simulation
If you add the new test, and then use the Reference History toolbar to reference the previous history that ran with the other tests, it can avoid repeating simulations for tests/corners that have already run. I suggest you try it out on something small to ensure you understand how it works. Regards, Andrew.
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