Hi Samir, The code in this article on support.cadence.com does what you want. Unfortunately the UI part doesn't work properly currently - you're supposed to be able to specify the number of waveforms on the stack to use. That's been broken for a while (I have a CCR for this), but to be honest I'd sooner this moved to the newer calculator template capability that was introduced in the IC617 release. That doesn't yet support a variable number of waveforms (I have a request for that too), so for now you'd have to type in the expression: abGroup(VT("/OUTM") VT("/OUTP") VT("/INM") VT("/INP")) which will convert the four (or however many) waveforms into a family (or fix the expression after using the abGroup function in the calculator panel having registered it). Regards, Andrew.

Often when doing RF structures I need a cline where one end is connected to ground (grounded stub). The way I have been doing it is to add a static GND shape on the layer I need to connect to, and then do a net short operation to the cline. This way becomes a bit tedious and messy once the number of these RF grounded stubs gets high - so I was wondering if anyone has found a better way to do this? The mess comes mostly from the large number of static solid shapes on the ground layer, waived DRC or multiple net short operations when counting vias and the need to modify as you go.

Hi, I have convergence issues even if I run very simple inverter circuit with fdsoi 28nm technology. Here I paste the schematic. As you see I tried to generate VSS=0 myself but still I have problem. Meanwhile, I paste my netlist and all the errors and warnings here. I can not understand why I have these errors. Thank you for your help. NETLIST // Generated for: spectre // Generated on: Nov 26 13:56:39 2018 // Design library name: SRAM1_13_11_2018 // Design cell name: testbench_26_11_2018 // Design view name: schematic simulator lang=spectre global 0 vss! VDD! include "models.scs" include "/home/azamolss/28nm/setup_working_dir/corners.scs" // Library name: SRAM1_13_11_2018 // Cell name: test_26_11_2018 // View name: schematic subckt test_26_11_2018 INPUT OUTPUT vdd vss P0 (OUTPUT INPUT vdd vdd) lvtpfet w=80n l=30n as=6.08f ad=6.08f ps=232n \ pd=232n nf=(1)*(1) sa=76n sb=76n sd=96n ptwell=0 par=1 sca=-1 \ scb=-1 scc=-1 pre_layout_local=-1 p_la=0 lpccnr=0 covpccnr=0 \ ngcon=1 wrxcnr=0 nsig_delvto_uo1=0 nsig_delvto_uo2=0 soa=1 swshe=0 \ swrg=1 mismatch=1 m=1 xpos=-1 ypos=-1 plorient=1 plsnf=0 N0 (OUTPUT INPUT vss vss) lvtnfet w=80n l=30n as=6.08f ad=6.08f ps=232n \ pd=232n nf=(1)*(1) sa=76n sb=76n sd=96n ptwell=0 par=1 sca=-1 \ scb=-1 scc=-1 pre_layout_local=-1 p_la=0 lpccnr=0 covpccnr=0 \ ngcon=1 wrxcnr=0 nsig_delvto_uo1=0 nsig_delvto_uo2=0 soa=1 swshe=0 \ swrg=1 mismatch=1 m=1 xpos=-1 ypos=-1 plorient=1 plsnf=0 ends test_26_11_2018 // End of subcircuit definition. // Library name: SRAM1_13_11_2018 // Cell name: testbench_26_11_2018 // View name: schematic I6 (net7 net2 VDD! vss!) test_26_11_2018 V0 (net7 0) vsource type=pulse val0=0 val1=1 C0 (net2 0) capacitor c=50f V3 (0 vss!) vsource dc=0 type=dc V4 (VDD! 0) vsource dc=1 type=dc simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf tran tran stop=20n errpreset=conservative write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=allpub subcktprobelvl=2 And here is the errors and warnings: Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 13.1.1.117.isr8 64bit -- 19 Jun 2014 Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: azamolss Host: venus.tele.ntnu.no HostID: F1814302 PID: 14215 Memory available: 132.6755 GB physical: 135.4257 GB CPU Type: Intel(R) Xeon(R) CPU E5-2640 0 @ 2.50GHz Processor PhysicalID CoreID Frequency Load 0 0 0 2499.9 2.2 1 1 0 2499.9 0.2 2 0 1 2499.9 2.3 3 1 1 2499.9 0.2 4 0 2 2499.9 0.2 5 1 2 2499.9 0.0 6 0 3 2499.9 0.1 7 1 3 2499.9 0.0 8 0 4 2499.9 0.0 9 1 4 2499.9 0.0 10 0 5 2499.9 0.3 11 1 5 2499.9 0.0 Simulating `input.scs' on venus.tele.ntnu.no at 2:08:01 PM, Mon Nov 26, 2018 (process id: 14215). Current working directory: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist Environment variable: SPECTRE_DEFAULTS=-I. Command line: /eda/tools/cadence/mmsim.13/tools/bin/spectre -64 input.scs \ +escchars +log ../psf/spectre.out -format psfxl -raw ../psf \ +lqtimeout 900 -maxw 5 -maxn 5 Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ... Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ... Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ... Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ... Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/input.scs Reading link: /eda/tools/cadence/mmsim.13 Reading file: /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/configs/spectre.cfg Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/models.scs Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/setupCornersIncludeFile.scs Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/importNetlist.scs Reading file: /home/azamolss/28nm/setup_working_dir/corners.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_beol.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_feol.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_fet.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_varactor.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_varind.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_cmim16acc.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_esd.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_2t8x_lb.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/soa.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_2t8x_lb_wo_via.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2t8x_lb.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2t8x_lb_wo_via.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2u2x_2t8x_lb.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2u2x_2t8x_lb_wo_via.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_1t8x_lb.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_1t8x_lb_wo_via.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/driftotp.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cvar_eg.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/pnpv.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/npnv.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_5U1x_2T8x_LB.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_5U1x_2T8x_LB.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_6U1x_2T8x_LB.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_6U1x_2T8x_LB.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_6U1x_2U2x_2T8x_LB.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_6U1x_2U2x_2T8x_LB.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmim16acc.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/matching.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rvt.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/eg.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsd.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsw.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsv.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsl.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsp.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsv.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egncap.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egpcap.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rpolyp.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rpolyh.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rndiff.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rnwell.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/diode.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rmetal.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/eglvt.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/grhcdsti.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/grhcdgated.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hcdgated.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hcdsti.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rvtnfetsb.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egnfetsb.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/sblkndres.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/sblkpdres.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hlvt.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsx.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egext.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_rf_custom.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/veriloga.scs Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va Reading link: /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/constants.h Reading file: /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/ahdl/constants.vams Reading link: /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/disciplines.h Reading file: /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/ahdl/disciplines.vams Warning from spectre during AHDL read-in. WARNING (VACOMP-2266): "$stop; 20 ns) ************************************************ Trying `homotopy = gmin' for initial conditions. Trying `homotopy = source' for initial conditions. Trying `homotopy = dptran' for initial conditions.. Trying `homotopy = ptran' for initial conditions.. Trying `homotopy = arclength' for initial conditions. None of the instantiated devices support arclength homotopy. Skipping. Error found by spectre during IC analysis, during transient analysis `tran'. ERROR (SPECTRE-16385): There were 7 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is I(V4:p) = 1.58867 GA, for which the quantity is `I' and the blowup limit is (1 GA). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value. ERROR (SPECTRE-16080): No DC solution found (no convergence). The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given. Failed test: | Value | > RelTol*Ref + AbsTol Top 10 Residue too large Convergence failure: V(I6.N0.gi) = 0 V residue too large: | -486.935 nA | > 43.0633 nA + 1 pA The following set of suggestions might help you avoid convergence difficulties. After you have a solution, write it to a nodeset file by using the `write' parameter, and read it back in on subsequent simulations by using the `readns' parameter. Evaluate and resolve any notice, warning, or error messages. Perform sanity check on the parameter values by using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value by using `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes. Enable diagnostic messages by setting option `diagnose=detailed'. Small floating resistors connected to high impedance nodes can cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file, and set as many nodes as possible. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable. If simulating a bipolar analog circuit, ensure that the region parameter on all transistors and diodes is set correctly. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence. If the analysis fails at an extreme temperature, but succeeds at room temperature, try adding a DC analysis that sweeps temperature. Start at room temperature, sweep to the extreme temperature, and write the final solution to a nodeset file. Increase the value of gmin (on options statement). Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to a value in the range of 0.1 to 0.5 by using `pivrel' (on options statement). Try to simplify the nonlinear component models to avoid regions that might contribute to convergence problems in the model. Divide the circuit into smaller pieces and simulate them individually. However, ensure that the results are close to what they would be if you had simulated the whole circuit. Use the results to generate nodesets for the whole circuit. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when none of the signals in the circuit are changing) and write the final point to a nodeset file. To make transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach fails or is very slow because the circuit contains an oscillator. Often, for finding the dc solution, the oscillation can be eliminated for by setting the minimum capacitance from each node to ground (`cmin') to a large value. Analysis `tran' was terminated prematurely due to an error. finalTimeOP: writing operating point information to rawfile. Error found by spectre during DC analysis, during info `finalTimeOP'. ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point. Analysis `finalTimeOP' was terminated prematurely due to an error. ****************** DC Analysis `dcOp' ****************** Error found by spectre during DC analysis `dcOp'. ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point. Analysis `dcOp' was terminated prematurely due to an error. dcOpInfo: writing operating point information to rawfile. Error found by spectre during DC analysis, during info `dcOpInfo'. ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point. Analysis `dcOpInfo' was terminated prematurely due to an error. modelParameter: writing model parameter values to rawfile. element: writing instance parameter values to rawfile. outputParameter: writing output parameter values to rawfile. designParamVals: writing netlist parameters to rawfile. primitives: writing primitives to rawfile. subckts: writing subcircuits to rawfile. Aggregate audit (2:08:04 PM, Mon Nov 26, 2018): Time used: CPU = 2.16 s, elapsed = 3.39 s, util. = 63.8%. Time spent in licensing: elapsed = 69.4 ms. Peak memory used = 69.5 Mbytes. Simulation started at: 2:08:01 PM, Mon Nov 26, 2018, ended at: 2:08:04 PM, Mon Nov 26, 2018, with elapsed time (wall clock): 3.39 s. spectre completes with 5 errors, 11 warnings, and 2 notices.

Your post got held up in moderation because it contains a lot of repeated text, which fooled the spam detector into thinking it was spam. I released it from moderation. I suggest you contact customer support , because this will need access to the specific PDK models to understand what is going on. I just put in some faked models and the simulation runs successfully - looking at the circuit, there doesn't seem anything out of the ordinary. Before contacting customer support, I'd suggest: Try running with the latest SPECTRE version (either SPECTRE17.1 latest hotfix or SPECTRE18.1 latest hotfix). This is using the utsoi2 model and I did find some reports of issues with the UTSOI2 model which were fixed in more recent versions than the one you're using (some fixes in a SPECTRE16.1 hotfix, for example). I did find an outstanding issue due to a self-heating effect which was awaiting a fix from the model developers, but I'm guessing this may not be your problem. Either way, it's worth using a more recent spectre version than one from 4.5 years ago... Make sure you have the latest models from the foundry. Regards, Andrew.

That pulse source hasn't a DC value assigned and timing/freq parameters are missing. I am not sure what Spectre is using here for the DC solution, worst case it is open and you have a floating gate.

there is a command DboState in the TCLextensions document. anyone can explain it ? . what's mean about it ?

Hi! I want to automate the plotting of sampled PNOISE and PXF results, but for these simulations the getData() function expects an argument "eventtime" (corresponding to the sampling event(s) found in the PSS run). How can I determine the values getData() expects for "eventtime"? I tried determining them manually using the cross() and list() calculator functions, but the results don't match the string values (or list of string values?) getData() expects due to rounding / number format mismatches (e.g. for the same point the calculator returns 33.0776972388E-12, while getData() expects '3.30777e-11). Thanks and regards, Jorge

Marc, In the absence of a DC value, a pulse source would normally use the time zero value. Since there's no obvious timing values specified, time zero value would be whatever val0 was. Even in the absence of these parameters, the dc value defaults to 0V. So it would never be floating - so that's not the reason. In this case val0=0 so it would be a 0V source. Regards, Andrew.

Hi Jorge, sweepVarValues("eventtime" ?result 'pxf) For newer pnoise where you have the jitter(sampled) mode, you'd have to use something like: sweepVarValues("jittereventtime" ?result 'pnoise_sample_pm0) The output result database name has changed, and it's called jittereventtime rather than eventtime - but the principle is the same. Regards, Andrew.

Hi Andrew, thanks for your prompt reply! I tried sweepVarValues("eventtime" ?result 'pxf) for a pxf triggered in both rising and falling events (thus 2 crossings), and the calculator gives me the following output: complex(33.0777E-12,157.921E-12) which is weird (the documentation says sweepVarValues() should return a list). Moreover, when trying to embed this into the real() and imag() functions, the calculator refuses to produce an output. I mean: imag(complex(33.0777E-12,157.921E-12)) works but imag(sweepVarValues("eventtime" ?result 'pxf)) fails. Any ideas on how to solve this? (and also, how to convert the result to a list (or symbol?) to pass to getData()?) Thanks and regards, Jorge.

Thanks so much for your prompt reply, Andrew! After some trial and error I got it working (got messy with the output returned by sweepVarValues()). For a 2-event (rising and falling edges) sampled PXF simulation, I got the instants using the following expressions: Trising_edge = car(sweepVarValues("eventtime" ?result 'pxf)) Tfalling_edge = cadr(sweepVarValues("eventtime" ?result 'pxf)) Note: strangely enough, entering sweepVarValues("eventtime" ?result 'pxf) on the calculator returns the instants as a complex number (!) Thanks again for your help! Regards, Jorge.

Hi Jorge, Yes, for some strange reason the calculator interprets a list of two numbers as a complex value despite there being an explicit complex type. I’m not sure why. Was about to say that you can do: value(getData(“/V0” ?result ‘pxf) “eventtime” car(sweepVarValues(“eventtime” ?result ‘pxf))) but you’ve worked that out (can use cadr for the second event). If more than that you could use the nth or nthelem functions to pull out the nth crossing events (nth uses indexing starting from 0 and nthelem starts from 1). Regards, Andrew

Great, thanks for the info!. Just one follow up: for PXF the wave returned by getData() seems to preserve the separation by sidebands, so when I try to evaluate "the full curve" at a particular point with value(), it returns multiple crossings (one per for each sideband--I guess for the ones which actually don't include the evaluation frequency, it's interpolating). Is there a way to "combine" or "fuse" the different sidebands in the object returned by getData(), so as to produce a "consolidated" waveform that can be properly evaluated with value()? Thanks again, Jorge.

Hi Andrew, Thanks a lot!

Jorge, Quick answer as plane about to take off. You should use the harmonic function to pull out the sideband you want first and then you’ll have a simple value vs frequency curve that you could use cross on. Regards, Andrew

OK, thanks so much! Enjoy your flight!

Thanks for tips! They helped a lot. I was able to create it.

Up until now, the company I work for has only used one pcb fab/assembly house and there hasn't been any problem meeting their design rules. But now there is a push to have a second source for our pcb assemblies. The problem is that the new fab house has a different set of footprint requirements and of course the existing ones we generally use do not meet these new requirements. I'm sure that this must come up in the industry from time to time and I'm curious to see how others are handing it. Any thoughts? I am using Allegro DE-HDL and the Allegro PCB editor.

Hi, Yep, this does comes up from time to time. There are ways to combat this however. One, try building parts per the IPC specifications if you can. They should not have issues with IPC footprints. Now if you have non- IPC footprints and data from another production supplier stating good soldering quality. Then try to insure the new supplier your parts will solder up fine. Suppliers prefer going with their own footprints because they know they will work. Your footprints are a mystery to them.That's why they are giving you a hard time. So, in this case. Tell them to assemble a small quantity of your boards to verify footprint solder ability. If, parts solder fine the supplier should green light you for a full production run . If parts solder up with issues. Then they still needs to tell you why they cant match the quality reported from your previous supplier. After all of this it becomes risk management for both you and the supplier. How much to want to pay for rework if any?? Cheers

Hello, Simple question: I want to plot Plotting Ids vs Vgs in Cadence of a transistor but I want Y Axis to be Square Root of IDS - how do I plot this in Cadence Virtuoso/Spectre using the ADE and Calculator ? Thank you.