Hi All, I have a transistor level description of a custom standard cell which is made of pass transistors and transmission gates. As can be seen, since the input buffering (i.e. an inverter) is missing (i.e. input B) in this type of a cell, the input capacitance seen at B input depends on the capacitive load presents at the output. How can we indicate this to Liberate and make the input capacitance of the cell a function of output load capacitance instead of a fixed value ? Thanks in advance Anuradha
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Forum Post: Input Capacitance Characterization in Cadence Liberate
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Forum Post: RE: Cadence Liberate Characterization of Complex Logic Cells
Dear Guangjun, Could you please kindly take a look at the following post made : community.cadence.com/.../input-capacitance-characterization-in-cadence-liberate
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
Hi, This is not a normal standard cell, and you may have different issues if you want to characterize it. Can you find specifications for cells of such a nature, ie. a transmission/pass gate, in the Liberty documentation? For the specific question you raised here, please read the liberate manual on harness. It might or might not work. basically, you may put any external components into a harness. Regards, Guangjun
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
Thanks alot for your reply. My question should be, rather, how to characterize such a cell. From the manual, following seem to be related to this type of behavior : However, it's bit unclear how these switches should be used in the script and whether they satisfy my requirement. I'll look for the "Harness" in manual..... Anuradha
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
Hi Again, These settings are for CCSN noise model. Regards, guangjun
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Forum Post: QRC: extraction fails due to ports names including the "+" character
Hi! The QRC extraction of various cells is failing due to them having port names that use the "+" character. For example, In the QRC log file I get: +ERROR (LBMISC-215479): at "agds2rcx": syntax error in file /path/to/my/svdb/my_cellname.ports because of an invalid character '+' at line 12 (and in the my_cellname.ports file I see that line corresponds to the entry associated to a port named "clock_latch_N+1"). Is is possible to make PVS/QRC support these port names with the "+" character? We have many cells affected by this, so we'd like to avoid the pain/risk of changing them now (tapeout time). Thanks and regards, Jorge.
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Forum Post: How to select object based on shape
Hi All, I want to select the object(Pin, Via & Symbol) based on the shape. please help on this. Regards, Sakthivel
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
Hi Guang, one of the harness example codes in the manual is shown below: https://pastebin.com/QZrD6Xb6 1. What do " Xdriver0_1" and "I0_altos_tmp" represent ? altos_in, altos_out and altos_stim were explained in the manual. 2. In this example, the input stimulus to the target cell seems to be an inverter. But what does the "order" mentioned in number 3. imply ? Are vdd, vss and INV_1 assigned to other 3 terms respectively ? * driver for pin I1, * I1_altos_stim - > I1_altos_tmp - > I1_altos_in Xdriver1_1 I1_altos_tmp I1_altos_stim vdd vss INV_1 3. Although the cell behavior is similar to my case (un-buffered), I cannot find a diffinition of input capacitance in the cell or any .subckts. So in this case, is the input capacitance of target cell neglected or considered to be driving inverter input capacitance (Both not accurate) ? 4. Under "harness parameters", _cap definition is there for output loads. There is no way to define the input cap though ! Anuradha
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
1. Xdriver* are instance names in the actual external driver in this example. 2. The example is just to show you how to define a harness to bias/load a cell with external circuit. Actual content will depend on your case. 3. I do not see any similarity here. generally speaking, a transimisson/pass gate does not have a liberty model, as this is not documented in Liberty specification. 4. I was hoping you can use a harness to include the elements, so that the actual capacitance will be simulated during your Liberate run. Guangjun
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
[quote userid="178062" url="~/cadence_technology_forums/f/custom-ic-design/41182/input-capacitance-characterization-in-cadence-liberate/1359105#1359105"]4. I was hoping you can use a harness to include the elements, so that the actual capacitance will be simulated during your Liberate run.[/quote] If this cell is used for a well defined design, I can define the right output capacitance to the cell using a harness (As I know the exact capacitive load that connects to the cells output). But during the synthesis, the capacitive load to any cell bound to change, so that assigning a fixed load during a characterization does not help. Instead the "input capacitance" should be decided from kind of a look up table or something depending on the attached load. If there is a harness parameter for input cap i.e. _cap, I can directly assign out_cap to be in_cap in harness subckt block (instead of letting it to be a fixed value). May be this is not doable. Anuradha
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
From what I understand, the input capacitor come from contribution of other active devices. That's why I suggested you to try harness. with this approach, the devices in the harness will be included/simulated during the charatcerisation. If the input cap has fixed values depending on external port condition, you can also create a wrapper cell with the same name as the cell to be characterized. inside the wrapper, you can use spice commands to assign a different value based on external port condition. you will have to make sure the simulation can run successfully. Guangjun
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
Apart from introducing harness blocks, is there a way we can interfere into the "capacitance measurements" of a pin in liberate ? Instead of a fixed single value, to define a range of capacitances depending on i.e. an external condition ? So that in generated .lib file (shown below) : pin (A) { direction : input; related_ground_pin : VSS; related_power_pin : VDD; max_transition : 0.56; capacitance : 0.0289202; rise_capacitance : 0.0289202; rise_capacitance_range (0.000516565, 0.0289202); fall_capacitance : 0.0287069; fall_capacitance_range (0.000516728, 0.0287069); I want to say that pin A capacitance value (0.0289 - in this case quite higher since no input buffering), should be depending on output load. In other words, use the right input capacitance for input A (from rise_capacitance_range) depending on the output load. To the best of my knowledge, rise/fall capacitance range of this type of cell highly depends on output conditions. Anuradha
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
I am not sure that I understand your question(s) now. If you can characterise the arcs successfully, a harness will be the best way to account for non-linear capacitance contributed by external component---This has never be clarified by you. It is not clear to me what you meant or wanted with the last example. The default syntax with liberate-generated library is like the example. If you want to post-processing some attributes/values, you can use the user_data flow (please refer to write_userdata_library and search for other user_data, if needed). Or, you may try set_attribute command. Guangjun
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Forum Post: Quantus: warning regarding separate field solver techfile with MEOL stack description
Hi! I am getting the following warning when performing Quantus extractions with the FS extraction mode: WARNING (NEBULAM-135092): Design is using device stack extraction in 'TSMC finfet' node. Foundry is supposed to provide separate field solver techfile with MEOL stack description. With current techfile you are not going to get sign-off certified accuracy for nets connected to MEOL devices. If you do have FS technology file and still see this warning request Cadence support to recover accuracy. Do I need to have some additional decks installed in order to use the FS extraction mode? I am using Quantus 18.2.1-s210 on TSMC 16FF+ PDK. Thanks and regards, Jorge.
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Forum Post: RE: Plotting transistor parameters in a temperature sweep
That works perfectly! Thanks. You know - I'm hoping that people spending their vacations helping me out is a trend that catches on. The world needs more people like that (until I retire) ;-).
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Forum Post: Liberate - Custom Cell Characterization
Tools and Tech: ST 65nm | LIBERATE Library Characterization Platform (x86_64) 12.1.4 (altos 121) | Cadence Virtuoso 6.1.5-64b | Calibre Interactive - PEX v2012.4_16.11 I am trying to characterize a full custom designed cell. Parasitics are extracted using Calibre Interactive - PEX v2012.4_16.11. The extracted netlist is CELL.pex.spi from pexRunDir using Calibre PEX tool. Technology Model Files created using: ADE L environment --> ArtistKit --> Setup Corners ... --> Model File --> Show Corners --> File --> save as ... which is corners.scs for spectre simulator The problem is that Liberate tool does not write any *.lib file out and no error or log file is generated by Liberate so that I can find the issue out? Any Idea how to proceed or solving the issue? Any better or even the corret way of getting extracted netlist and model files? The simple script which I use comes from example codes of liberate and Virtuoso Liberate Reference Manual 18.1 set ROOT "/home/PROJECT" source ${ROOT}/PATH.tcl source ${CHAR_SCRIPT}/parameters.tcl set MODEL_TYPE spectre set_operating_condition -voltage ${my_voltage} -temp ${my_temperature} source ${CHAR_SCRIPT}/template_example.tcl read_spice -format spectre ${CHAR_MODELS}/${MODEL_TYPE}/${MODEL_TYPE}_corners_ss.scs set spicefiles ${CHAR_NETLIST}/Inv.pex.spi read_spice $spicefiles char_library write_library TTTT.lib
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
Hi Guang, I used the "harness" in cell and defined a custom output loads. The characterization log file is shown below: https://pastebin.com/u5z3YD4d For some reason, it first states "passing all cells" and at the end of the run prints "bad ccs data found...". I tried convert the .lib file to a .db and then conversion too also complains that some timing arcs were missing in .lib. Well I started with assigning a reasonable cap load to the output terminals. Any idea what went wrong in this ? Thanks Anuradha
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Forum Post: RE: Input Capacitance Characterization in Cadence Liberate
are we still talking about the same cell? if so, you will not be able to get a valid ccs mode for such a cell. CCS model creation relies on the related PG pins, which does not exit in your case. Guangjun
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Forum Post: RE: Import Schematic from Mentor Tanner to Cadence
This is what I got after keying in file Project_design.edf: Project_design.edf: ASCII text, with CRLF line terminators The next line, head -2 Project_design.edf|cat -vet: (edif Project_design^M$ ^I(edifVersion 2 0 0)^M$
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Forum Post: Latest version of Hot Fix for Alllegro 17.2
Hello, Can someone let me know the latest version of hot fix for 17.2 ? thank you
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