sstatus(fullPrecision nil) atof("9.12") => 9.12 You didn't state what fullPrecision is currently set to, but I expect that it was set to 't', so setting it to 'nil' should give you the above result. Regards, Lawrence.
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Forum Post: RE: What setting will impact atof() output
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Forum Post: RE: What setting will impact atof() output
Works well. Thanks a lot!~
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Forum Post: RE: How about 8L ELIC HDI?
Cool! Looks nice!
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Forum Post: RE: Mechanical Hole to Dynamic Shape Spacing
Can't see your board but dynamic shapes to mech holes will follow the MECH_PIN_TO_CONDUCTOR_SPACING rule that is in Constraint Manager->Analyze->Analysis Modes Once in that menu, it's under Design->Mechanical Spacing->Mechanical Drill to Conductor Spacing
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Forum Post: ComponentDefinitionProps documentation
Hello, I was looking for a piece of documentation about the fields that fall under ComponentDefinitionProps but wasn't able to find any. I had some problems the CLASS field at some point and I am wondering what are the valid values for this field. However, the question is generic and applies to all the predefined fields under ComponentDefinitionProps. Regards, Catalin
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Forum Post: ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre
Hi, I am trying to simulate a basic inverter circuit using spectre. I have generated a netlist file. when I run it, I am getting the following error ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 2: Unexpected end of line. Expected equals sign, numeric value or string value. For your referrence, I am posting the files 'cds.lib', 'input.scs' and 'spectre.out' here. Can someone help me out. Thanks in advance *************cds.lib******************** #Following defined by Chandrasekhar DVS DEFINE analogLib /usr/local/IC614/tools/dfII/etc/cdslib/artist/analogLib DEFINE US_8ths /usr/local/IC614/tools/dfII/etc/cdslib/sheets/US_8ths DEFINE basic /usr/local/IC614/tools/dfII/etc/cdslib/basic DEFINE cdsDefTechLib /usr/local/IC614/tools/dfII/etc/cdsDefTechLib DEFINE NCSU_TechLib_FreePDK15 $PDK_DIR/cdslib/NCSU_TechLib_FreePDK15 DEFINE ADETutorial /home/eslam/ADETutorial_1/ADETutorial DEFINE SPECTRE_TUTORIAL /home/eslam/ADETutorial_1/SPECTRE_TUTORIAL #DEFINE analogLib $CDS/IC/tools/dfII/etc/cdslib/artist/analogLib #DEFINE US_8ths $CDS/IC/tools/dfII/etc/cdslib/sheets/US_8ths #DEFINE basic $CDS/IC/tools/dfII/etc/cdslib/basic #DEFINE cdsDefTechLib $CDS/IC/tools/dfII/etc/cdsDefTechLib ***************************************** ************* input.scs**************** // Generated for: spectre // Generated on: Apr 21 11:31:37 2019 // Design library name: SPECTRE_TUTORIAL // Design cell name: myInverterTB // Design view name: schematic simulator lang=spectre global 0 vdd! parameters VDD_VAL=0.8 include "/home/eslam/ADETutorial_1/cds.lib" // Library name: SPECTRE_TUTORIAL // Cell name: myInverter // View name: schematic subckt myInverter I O inh_bulk_n inh_bulk_p I2 (O I inh_bulk_p inh_bulk_p) pmos I6 (O I inh_bulk_n inh_bulk_n) nmos ends myInverter // End of subcircuit definition. // Library name: SPECTRE_TUTORIAL // Cell name: myInverterTB // View name: schematic I5 (IN OUT 0 vdd!) myInverter V0 (vdd! 0) vsource dc=VDD_VAL type=dc V1 (IN 0) vsource type=pulse val0=0 val1=VDD_VAL period=20p delay=0 \ rise=1p fall=1p width=9p C0 (OUT 0) capacitor c=1f simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf tran tran stop=40p write="spectre.ic" writefinal="spectre.fc" \ annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save IN OUT saveOptions options save=allpub ********************************************************** ***************spectre.out************ Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 7.1.1.187.isr11 32bit -- 18 Aug 2009 Copyright (C) 1989-2009 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782; 7,085,700; 7,143,021; 7,493,240. Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: root Host: localhost.localdomain HostID: 7F0100 PID: 5290 Memory available: 1.0215 GB physical: 1.9854 GB CPU(1 of 2): CPU 0 Intel(R) Core(TM)2 Duo CPU T6600 @ 2.20GHz 2200.000MHz Simulating `input.scs' on localhost.localdomain at 11:40:05 AM, Sun Apr 21, 2019 (process id: 5290). Environment variable: SPECTRE_DEFAULTS=-E Command line: /usr/local/IC614/MMSIM/tools.lnx86/spectre/bin/32bit/spectre \ input.scs +escchars +log ../psf/spectre.out +inter=mpsc \ +mpssession=spectre0_3079_6 -format sst2 -raw ../psf +lqtimeout \ 900 -maxw 5 -maxn 5 spectre pid = 5290 Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ... Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ... Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ... Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ... Error found by spectre during circuit read-in. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 2: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 3: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 4: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 5: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 6: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 7: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 8: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 9: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 10: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 11: Unexpected end of line. Expected equals sign, numeric value or string value. ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 13: Unexpected end of file. Expected equals sign, numeric value or string value. Time for parsing: CPU = 195.97 ms, elapsed = 347.244 ms. Time accumulated: CPU = 243.962 ms, elapsed = 348.989 ms. Peak virtual memory used = 552 Mbytes. Aggregate audit (11:40:06 AM, Sun Apr 21, 2019): Time used: CPU = 245 ms, elapsed = 350 ms, util. = 69.9%. Time spent in licensing: elapsed = 177 ms, percentage of total = 50.5%. Virtual memory used = 552 Mbytes. spectre completes with 11 errors, 0 warnings, and 0 notices. spectre terminated prematurely due to fatal error. *********************************************************
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Forum Post: simulating node capacitance charging
Hello , i am trying to build an RF frequency D FlipFlop as shown bellow. On the node Q signed by blue arrow i get a very abnormal charge and discharge behavior. On the first TG opening Q charges half the way. When TG closes, it charge Q till the end although its not suppose to charge at all at this step(closed TG) ,as shown in the last plot bellow. Is there a way to see how much capacitance we have on node Q when TG opens? Thanks.
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Forum Post: RE: ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre
By the way, your post went into moderation because it contained lots of repeated text, which is often a sign of spam. As soon as I'd reviewed it (after your feedback) I let it through. Two things here: You appear to be referencing the cds.lib in the Setup->Model Libraries in ADE. That makes no sense, because the cds.lib does not contain the definitions of the Spectre models, but instead is the definition of the library names used by Virtuoso for schematics, layouts etc. You need instead to reference the transistor models (which define the models for nmos, pmos etc). These probably will be in the PDK setup somewhere and have a .scs suffix, and if you look in the file will contain either "model nmos" or "subckt nmos" lines. You're using very old versions of the tools. Spectre 7.1 is from 10 years ago, and Virtuoso IC614 is probably a similar age (I can't remember off the top of my head, but we've had 4 major IC versions since then, and 10 major versions of Spectre). Why are you using such ancient versions? That's a little bizarre - even for a university. Regards, Andrew
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Forum Post: RE: Skill languag(beginner level)
Yes, the layer in which the label is specified is the IP layer. It has a prefix of &. Example is "& Date_Time 20190114". I have to find this label and then modify it accordingly.
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Forum Post: RE: simulating node capacitance charging
You could use the captab capability to report the instantaneous capacitance operating point info at the the times in question. The easiest way to do this is first to enable a dc analysis with the captab settings (strictly speaking it's not the DC analysis, but an info analysis, and so you could potentially use a row in the Save circuit information analysis table to add a new captab output - but for now I'll just showing doing it from dc). This is on the DC options form: Then on the transient options form, enable infotimes to be the times you want to output the capacitance info - and give the name of the captab info analysis (the name is generated automatically by checking the captab on the DC options above - the name I've given here is the name that appears in the netlist): Then after running the simulations, under Results->Print->Capacitance Table you'll get this - with a cyclic field at the top to pick the time you wish to look at: Regards, Andrew.
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Forum Post: RE: ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre
Thank you Andrew. The input.scs files correspoding to models nmos and pmos are not present in the NCSU_TechLib_FreePDK15 folder I downloaded from the site. is there anyway to generate one by myself? The following are the pictures that show the files present in the pmos and nmos directories. Also about the software version, our institute does not have one. We had to go out of state and are working via VMware, accessing cadence virtuoso. Thanks in advance.
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Forum Post: RE: pCell cyclic parameter CDF
Hi Rick, For a cyclic parameter you need to define choices in terms of the ?choices keyword parameter to cdfCreateParam(..). Max
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Forum Post: RE: Mechanical Hole to Dynamic Shape Spacing
Thanks, found it. Appreciate your input.
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Forum Post: RE: ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre
It appears that this kit only comes with HSPICE models - not necessarily a problem though - these can be used for Spectre as well. The models are not within the library itself, but in a directory above the place the library is located. The HSPICE models are at $PDK_DIR/hspice/models/fet.inc . However, the models are called pfet and nfet not pmos and nmos , so the first thing you'd have to do is edit the properties of your transistors and change the model name: (the same would have been true if you'd been using hspice as the simulator - this seems to be an inconsistency in the PDK). Then in ADE you can set this in the Setup->Model Libraries form: Ensure you pick "CMG" as the model section as that is the name of the library in the file. Having done that, I can run a simulation with the nmos and pmos components from the library. Regards, Andrew
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Forum Post: RE: Skill languag(beginner level)
Something like this would be a good basis of your code. The Technology label handling is just a suggestion to show what it might look like if you have labels such as "& Technology MyTech180": procedure(CCFupdateLabels(@key (cvId geGetEditCellView()) (layer "IP") (purpose "drawing")) let((lpp Date_Time Technology currentTime) currentTime=timeToTm(stringToTime(getCurrentTime())) ;---------------------------------------------------------------- ; Define any regular expressions needed to identify the labels ;---------------------------------------------------------------- Date_Time=pcreCompile("^& Date_Time") Technology=pcreCompile("^& Technology") ;---------------------------------------------------------------- ; Find the right layer purpose ;---------------------------------------------------------------- lpp=car( exists(LP cvId~>lpps LP~>layerName==layer && LP~>purpose==purpose) ) foreach(shape lpp~>shapes when(shape~>objType=="label" cond( ;---------------------------------------------------- ; Look for date labels - update to current time ;---------------------------------------------------- (pcreExecute(Date_Time shape~>theLabel) shape~>theLabel= sprintf(nil "& Date_Time %04d%02d%02d" currentTime->tm_year+1900 currentTime->tm_mon+1 currentTime->tm_mday ) ) ;---------------------------------------------------- ; Look for technology labels - update to current ; tech lib name ;---------------------------------------------------- (pcreExecute(Technology shape~>theLabel) shape~>theLabel= sprintf(nil "& Technology %s" techGetTechFile(cvId)~>libName ) ) ;---------------------------------------------------- ; Add other condition branches here ;---------------------------------------------------- ) ) ) t ) )
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Forum Post: RE: ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre
Thanks Andrew. All the previous errors disappeared but a new one appeared. It is as follows.
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Forum Post: Constraints in the schematic (DEHDL)
Hi, I'm using Cadence v17.2, Allegro Design Entry HDL for schematics and layout. At the moment, we have constraints at the schematic level (from an old design), and newer constraints in the layout. Is there a way to remove all constraints and board information from the schematic, to ensure that only the layout has control over these? (The problem arises from the layout engineer adding constraints required, but then when the schematic is updated, the 'old' constraints in the schematic file are read through and changes the latest layout ones! We've never had much success in the past ensuring the schematic and layout are in sync, and by default we only add constraints at the PCB level now to avoid this.... however, as this was an older design now in v17.2, I want to delete everything from the schematic side. Can it be done?! Thanks
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Forum Post: RE: ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre
Your spectre version is too old. Level 72 corresponds to bsimcmg, which didn't appear until MMSIM72 (2009) - the version after the one you're using. Expecting to simulate a FinFET design with 10 year old simulator technology is a bit optimistic... Mapping it to something else is not going to be that easy, since the number of fins is a parameter of this technology - so making up your own model is not going to work very well (nor is terribly realistic). You should contact whoever looks after the software installations you're using and ask them to install something more recent. Andrew.
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Forum Post: RE: Advice on moving forward. (I believe unit's of measurements caused an issue)
Glad I could help.
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Forum Post: RE: ERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated using ADE L, cadence Virtuoso v6.1.4 with spectre
Ok Andrew Thanks.
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