Thank you for the solution, I don`t know what the problem exactly was but I could fix it by Tools->Display Resources Manager->Merge... from the icfb menu.
↧
Forum Post: RE: Cadence schematic showing up all as yellow
↧
Forum Post: RE: shortcut to bring ADE with current schematic to front
Hi, how would you run it?
↧
↧
Forum Post: RE: shortcut to bring ADE with current schematic to front
For example add: hiSetBindKey("Schematics" " F2" "let((sess win) when((sess=sevSession(hiGetCurrentWindow())) && (win=sevWindow(sess)) hiRaiseWindow(win)))") in your .cdsinit . Then in the schematic you'd just hit the F2 key. Andrew.
↧
Forum Post: DELAY OF PARTICULAR PATH
I am dealing with design of multi bit adder. I am using the command 'report_timing -unconstrained' to calculate the delay of the design. This command is giving the delay of the critical path in the design. What is the command to be used inorder to get the delay of a particular input to output path, other than the critical path?
↧
Forum Post: RE: multi part path template files
Hi, Andrew. I'm using IC617 and I'm trying to create a template to draw 2 parallel 1um paths on comment layer, with a space of 0.8um and a all around halo of extra 0.8um. I managed to create the template and I can draw exactly what I need. My problem right now it's that I need to remove the halo (I only need it to keep the clearance while I draw the paths) and then somehow detach the 2 paths. I attached some images with the multipart settings and what it draws (for you to distinguish the halo, I moved it to another layer, just to have a different color in the attached picture). Can you please help me to advance with this? In the end, I only need those 2 separate paths. first path: second path: halo: result: Thanks.
↧
↧
Forum Post: RE: .CAD file extention
Rik, could you kindly explain, how to generate .CAD file from existing layout - using A17.2. THX Andreas
↧
Forum Post: RE: update instance cdf properties after storeDefaults changed
Hi Andrew, did you have the chance to write already this function and article? If yes could you please post here the link? It is useful for me and I believe it will be useful for many other users.
↧
Forum Post: Cannot add dummy net on No Connection pin
Hi, I need to put Dummy net on NC pin of a LED. But when i put Dummy net and try to assign to that pin it is showing "cannot assign dummy net to that pin". I need to put dummy net on that pin for heat dissipation. Thanks & Regards, K.Dinesh
↧
Forum Post: RE: Sweeping different design variables at the same time within an (qpss) analysis
I'm using Meastro. The workaround with the parentheses works great, thank you. I see, setting the frequency to 0 makes more sense to turn off a signal than giving it very low power. About the second edit: indeed these low powers doesn't make sense, it was a (non elegant) way to turn it off. Still I think there is a bug, entering an extremely low power in the power field (-10000dBm) shouldn't result in a tone of 10dBm.
↧
↧
Forum Post: VerilogA, one or the other parameter implementation
In for instance the port cell in analogLib you can enter for a certain signal either the Amplitude (Vpk) or the Amplitude (dBm). When one of them gets filled in, the other field blanks out. Is it possible to achieve the same using verilogA? If so how would this be implemented? Regards, Emiel
↧
Forum Post: getting an unknown error while using abeLayerXor in layout
Hi, I am trying to generate a layer in the regions of (don't overlap b/w two layers) .This are the steps i followed . This is giving an error saying *Error* abeLayerXor: First layer not correctly specified - nil Please let me know the issue tf=techGetTechFile(geGetEditCellView()) tf1=techFindLayer(tf 12) tf2=techFindLayer(tf 15) tf3=techFindLayer(tf 18) tf4=techFindLayer(tf 1090) tf5=techFindLayer(tf 1091) tf6=techFindLayer(tf 1092) tf7=techFindLayer(tf 1093) tf8=techFindLayer(tf 1117) tf9=techFindLayer(tf 1118) tf10=techFindLayer(tf 1130) tf11=techFindLayer(tf 236) tf12=techFindLayer(tf 59) abeInit(geGetEditCellView()) abeLayerXor(tf1 tf11 tf12) Thanks, Raghu
↧
Forum Post: RE: .CAD file extention
Try File - Export - Fabmaster out
↧
Forum Post: How to run the autorouter in Allegro 17.2?
When I attempt to autoroute, I get no routes done. Is there a special set-up I need to go through to get the Autorouter to work?
↧
↧
Forum Post: erf(), erfc(), normcdf() and friends in SKILL
By any chance has anyone implemented the error function and complementary error function in SKILL? I can use IPC to have octave (or other) do it behind the scenes but was wondering if there is an already complete pure-skill version. Thanks -Dan
↧
Forum Post: RE: shortcut to bring ADE with current schematic to front
Thanks. That would be great but if there are many schematic then you have to assign one shortcut key for each one? Like 5 schematics so 5 hotkeys? I am trying to find .cdsinit now.
↧
Forum Post: VLS lock manager auto-refresh without DM
Hello - we're trying to write a lock manager which shows the user what cells are currently write-locked in a certain library, by whom, and when the lock was created. We've got most of this in place already, including an option to release the write lock on a cell that you yourself have write-locked. We are not using any Design Management system - just a plain-ol OA library on disk that multiple people point to. As it is now, you have to manually refresh the locked file listing by clicking a button in the lock manager GUI. It would be excellent to get rid of that need: is there a good way to have the lock manager automatically refresh whenever a locked cell becomes unlocked, or when a previously unlocked cell gets locked by any user running on any node? ddRegTrigger("PreObjAccess" 'stuff) works for a single user's session; you would have to make sure that each user is running that trigger (and its callback function) and you'd also have to work some form of IPC to get them to notify each other of changes. Linux has some options like 'watch', which could also push out to all IPC listeners and would only have to run on one node, but it would be nice to not have a constantly running background application - but maybe it's not that computationally expensive? Is there some lower-level linux file system trigger that sends notifications on file/dir changes, which IPC could listen for, or even better, is there actually an already-existing SKILL function to do said listening? What's your recommended course of action for this type of listening? Thanks
↧
Forum Post: RE: Need some advice on how to complete this one microprocessor connection.
Hi, did you ever get the issue resolved with the padstack and run DB Doctor on the database ?. Seems like you got multiple issues going on with your board. On the copper pour, looking at the pictures I would say that on the new board the copper pour clearance rules are not the same as the prior board. This is the reason you have an island of copper. Carefully review your "Shape to" constraints under the spacing constraint set in the CM and see if they do indeed match the prior board. Look for shape to pin clearance etc. It will have to be fairly small to make a copper pour in or around those pins. If the shape spacing rules are the same in the CM as the prior board then it is possible that there is extra clearance getting applied beyond what is showing up in the constraint manager. Go to "Setup Design Parameters" and click on the shape tab.Next click "Edit Global dynamic shape parameters" Click on the clearances tab in there and see if any oversize values have been assigned to the shapes. BTW on your new board the cooper pour looks to be trying to connect to a pin but on the old board picture I am not seeing any connections from the copper pour to the pins shown ? Let us know what you find. All the best.
↧
↧
Forum Post: RE: [OrCAD PCB] Undo history constantly disappears
Hi I'm thinking this may be a bug. Perhaps open a ticket with tech support and see what they say.
↧
Forum Post: RE: 3D Viewer don't works
The 3D Viewer is working in S052. Maybe someone can chime in on S051
↧
Forum Post: RE: Unable to Route gridless in 17.2
Gridless is only used for pushing obstacles out of the way, for example while routing a trace next to a via the via will be pushed away but not snap to a grid. Traces snap to a grid while routing, Best solution is to reduce the grid size.
↧