Cadence Technology Forums

I have Orcad PCB Designer Standard 17.2 with the latest hotfix. I have placed all the components and routed the board. Design Status tells me I still have 42.6% Unplaced symbols. The Placement List shows many of the symbols. Those symbol show no coordinates if I run a Component report. But all those components have already been placed; I can see them on the board. If I try to place one of the duplicate components on the Placement List, the pads disappear from the already placed component, but the rest of the component is still there. If I try to move the added duplicate, the traces that were connected to the disappearing pads move. The attached picture shows an example: You can see that C6 and C7 are placed, but they are also in the Placement List and the Component report shows no coordinates. The .brd file is also attached. Please help!

Well, evidently the .brd file would not attach...

Hi, In the design entry hdl schematic, I'm not able to edit page name. Edit page name is disabled.Please help to resolve this.

Hi, I'm not able to edit page name in Schematic Design Entry HDL. The edit page name is disabled in schematics as shown below,

Hello Shawn,-60 ohm is not what we can expect from a formula like Z_L=jwL , wL cannot be negative. Furthermore its an idial inductor simulation, its not suppose to give me such noisy peaks only a straight line. Thanks

In explorer I dont find the option of using differential STB probes. I had the option in ADE L.

You need to probe an instance of diffstbprobe in your schematic - then you'll get the option on the form to pick the common-mode or differential-mode stability. The behaviour is the same between ADE L and ADE Explorer - you had to probe a diffstbprobe in ADE L too. Andrew.

Hi I want to auto generate series input.scs netlistS from series maestro viewS, then use the netlistS to do series EMIR analyses, and all the actions above need to be done under batch mode (-nogui way) I found a nearest functional API 'maeRunSimulation()' , it can generate input.scs I want but has no 'without simulation' option Is there some way to do this? THX

TITLE should be: How to generate input.scs from maestro view backgroud(-nogui way/batch mode)

The issue is that you have a very simplistic ideal network (with infinite Q) and it is highly sensitive to numerical error in calculating the Y parameters and your subsequent calculations based on the Y parameters. Simulators are not generally that good at dealing with ideal circuits because they are not optimised for that - but this would be a numerical problem anyway. Andrew.

Hi all, Backgroud: Mixed Signal block, with most implementation in Virtuoso, small controller block from digital. Problem: I have a top level post layout netlist with power and group pins from innovus. I want to use CDL file to define my gates in AMS simulator. Is that possible? The reason behind is, I want to use Spectre/APS to calculate my module power and delay for my block. Since pointing to verilog module my block behaves as ideal (no delay or power). I am aware of the fact that CDL is ment for LVS purpose only, but my understanding is if there is transistor level description I could use it. Please let me know if it this possible,if so where should I specified? I tried to specify it under setup --> simulation Files --> Definition files. It doesn't work. I also tried with generating cdl for my controller verilog file and including it as "Specify SPICE source File" in config view. But in that case, my netlist failed due to bus signal in my testbench [this method works well if I have only non-bus signals, and I am able to see delay/power consumption from the block] Please let me know if any more details required. Please let me know if there is any other method for the same. Thank you in advance. Regards,

Thanks Andrew. My memory not as good as it was once... Victor

See this post from May 10 BoardSurfers: Look Before You Leap - Verifying Footprints in the Design Capture Phase

Hello Andrew, actually what happened is that the cellview where ABC was being instantiated had a lot of floating nets and not all ABC's ports were connected. We fixed the schematic and the issue can be considered solved. Still, the message from the netlister is misleading, as it seems that the issue lies with ABC itself and not the schematic where it is instantiated. Also, it is not obvious what could make a terminal invalid. Anyway, thanks for the efforts and best regards, Patrik

Hi Patrick, Thinking about this, I suspect it may have been that you had the symbol instantiated when it had fewer pins originally, and then new pins were added later. the schematic containing the instance of ABC then had fewer instTerms and the missing terminals weren't there. Probably doing a check-and-save would fix it. You'd also get a warning when opening the schematic telling you that the symbol was newer than the last time it was checked. Anyway, glad you've solved it now. The above is just a wild guess without having seen the issue (so it might be something else altogether). Andrew.

Hello Andrew, is there a way to make the numerical calculation more strict and even if it will take more time it will get a more accurate result? Thanks

I would ask a different question - what is the point of doing this with an ideal inductor anyway? You know what the inductance is. One way you could compute it is a slightly different way: ; convert two-port to single port s11 s11_1port=spm('sp 1 1)-spm('sp 1 2)*spm('sp 21)/(1+spm('sp 2 2)) ; Convert s11 to z11 portImpedance=50 PI=3.14159265358979323 z11_1port=portImpedance*(1+s11_1port)/(1-s11_1port) L=imag(z11_1port)/(xval(spm('sp 1 1))*2*PI) plot(L) This is still a bit noisy, but the error is in the 15th/16th digit, so insignificant. Andrew.

Hi mrigashira , I just tried to do this and the "Show Footprint" command doesn't do anything. I wonder if it is because I have the tcl script (mentioned above in this thread) installed, and maybe it's blocking the integrated feature? Any ideas?

You have to zip it to attach here or put it on a share drive like Google or Github

community.cadence.com/.../ZuffaClock.zip Here is the .brd file

Forum Post: All components have been placed, but many are still on Placement List

Forum Post: RE: All components have been placed, but many are still on Placement List

Forum Post: Design Entry HDL

Forum Post: Edit Page Name disabled in Design Entry HDL

Forum Post: RE: Validate idial inductor using Yparam expression

Forum Post: Differential STB analysis in Explorer

Forum Post: RE: Differential STB analysis in Explorer

Forum Post: How to generate from maestro view backgroud(-nogui way/batch mode)

Forum Post: RE: How to generate from maestro view backgroud(-nogui way/batch mode)

Forum Post: RE: Validate idial inductor using Yparam expression

Forum Post: Simulating CDL netlist in AMS UNL

Forum Post: RE: Differential STB analysis in Explorer

Forum Post: RE: Footprint Viewer Not Present / Missing in OrCAD Capture 17.2

Forum Post: RE: Terminal in CDF termOder is invalid (CDL netlist)

Forum Post: RE: Terminal in CDF termOder is invalid (CDL netlist)

Forum Post: RE: Validate idial inductor using Yparam expression

Forum Post: RE: Validate idial inductor using Yparam expression

Forum Post: RE: Footprint Viewer Not Present / Missing in OrCAD Capture 17.2

Forum Post: RE: All components have been placed, but many are still on Placement List

Forum Post: RE: All components have been placed, but many are still on Placement List