while extracting topology of PL_DDR4_A0, the error as subject occured. but when i try to set pintype of R478.2 to UNSPEC, well, there is no such a thing as UNSPEC. possible types are: Bidirectional Input Output OpenCollector OpenEmitter Passive 3-state Power. what should i do?
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Forum Post: WARNING(ORCAP-40202): Pin '2' of comp 'R478' has PINUSE value other than UNSPEC.
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Forum Post: The veriloga code when simulted in cadence shows the following error. Thanks in advance.
While running the simulation of veriloga code in cadence, I am getting the following error. And, Also the second problem was that the parameter defined using the syntax "parameter real _____" is not being fed from the veriloga itself which I sorted out by manually entering the parameters in ADL XL. Error found by spectre during circuit read-in. ERROR (SFE-874): "input.scs" 10: Unexpected equals "=". Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045.scs Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_mos.scs Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_diode.scs Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_bipolar.scs Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_mimcap.scs Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_moscap.scs Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_resistor.scs Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_inductor.scs Reading file: /home/nano/DIC_project/S2d_new/veriloga/veriloga.va Reading file: /cad/MMSIM131/tools.lnx86/spectre/etc/ahdl/constants.vams Reading file: /cad/MMSIM131/tools.lnx86/spectre/etc/ahdl/disciplines.vams Time for NDB Parsing: CPU = 445.528 ms, elapsed = 499.365 ms. Time accumulated: CPU = 479.52 ms, elapsed = 499.371 ms. Peak resident memory used = 51.2 Mbytes. Time for parsing: CPU = 16 us, elapsed = 15.0204 us. Time accumulated: CPU = 479.685 ms, elapsed = 499.536 ms. Peak resident memory used = 51.2 Mbytes. Aggregate audit (4:50:55 PM, Sat Jun 1, 2019): Time used: CPU = 496 ms, elapsed = 516 ms, util. = 96.1%. Time spent in licensing: elapsed = 72.1 ms, percentage of total = 14%. Peak memory used = 51.2 Mbytes. Simulation started at: 4:50:54 PM, Sat Jun 1, 2019, ended at: 4:50:55 PM, Sat Jun 1, 2019, with elapsed time (wall clock): 516 ms. spectre completes with 1 error, 0 warnings, and 0 notices. spectre terminated prematurely due to fatal error. Below is the input.scs file corresponding to the simulation // Generated for: spectre // Generated on: Jun 1 14:58:29 2019 // Design library name: DIC_project // Design cell name: S2d_new_tb // Design view name: schematic simulator lang=spectre global 0 parameters LG=.1e-6 LOV=0 typ=1 Vgs0_e=.5 Vgs0_h=.5 Vbs0_e=0 Vbs0_h=0 \ m0=9.1e-31 meff_h_K= 5.8240e-31 meff_e_Q=5.733e-31 meff_h_Q=0 g_e_K=2 g_h_K=2 q=1.60218e-19 Eg_e= \ 2.8839e-19 Eg_h= 2.6917e-19 h_bar=105.457180027e-36 g_Q=6 E_KQ_h=0 Rch=200 Rce=200 eps=8.854187e-12 \ eps_t=1.1068e-10 TTOP=40e-9 eps_b= 3.4531e-11 TBOX=270e-9 FcH=100e6 FcE=20e6 W=1e-6 kox=1.4 Rcox=1.2e-8 ksi=140 L=.1e-6 \ Weff= 1.5400e-06 Rth_ox=.1360 Rth_int= 0.0120 Rth_si= 9.1008e-04 x=0 Eg=288.39z E_KQ_e= 2.0828e-20 meff_Q= 5.7330e-31 meff_K= 4.0950e-31 g_K=2 meff_e_K= 4.0950e-31 include "/cad/FOUNDRY/analog/45nm/gpdk045/../models/spectre/gpdk045.scs" section=mc // Library name: DIC_project // Cell name: S2d_new_tb // View name: schematic I0 (net4 net3 0) s2ds_120 str=1 typ=1 SELFHEAT=0 HIFIELD=0 GATEFIELD=0 \ version=1.1 W=1e-06 LG=1e-07 LOV=0 L=(LG)-((2)*(LOV)) TS=6.5e-10 \ TTOP=4e-08 TBOX=2.7e-07 tp=4e-08 Vgs0_h=0.5 Vgs0_e=0.5 \ Vgs0=((typ)==(1))?(Vgs0_e):(Vgs0_h) Vbs0_h=0 Vbs0_e=0 \ Vbs0=((typ)==(1))?(Vbs0_e):(Vbs0_h) m0=9.1e-31 \ meff_e_K=(0.45)*(m0) meff_h_K=(0.64)*(m0) \ meff_K=((typ)==(1))?(meff_e_K):(meff_h_K) meff_e_Q=(0.63)*(m0) \ meff_h_Q=0 meff_Q=((typ)==(1))?(meff_e_Q):(meff_h_Q) g_e_K=2 \ g_h_K=2 g_K=((typ)==(1))?(g_e_K):(g_h_K) g_Q=6 q=1.60219e-19 \ Eg_e=(1.8)*(q) Eg_h=(1.68)*(q) Eg=((typ)==(1))?(Eg_e):(Eg_h) \ h_bar=1.05457e-34 \ DOS_K=((meff_K)*(g_K))/(((3.14159)*(h_bar))*(h_bar)) \ DOS_Q=((g_Q)*(meff_Q))/(((3.14159)*(h_bar))*(h_bar)) \ E_KQ_e=(0.13)*(q) E_KQ_h=0 E_KQ=((typ)==(1))?(E_KQ_e):(E_KQ_h) \ Nimp=1e+14 Dtrap=1e+16 Etrap=(q)*(0.125) E0=(Eg)/(2) Vbs=40 \ Rch=200 Rce=200 \ Rc=(((0.5)*((1)-(typ)))*(Rch))+(((0.5)*((1)+(typ)))*(Rce)) \ eps=8.85419e-12 eps_t=(12.5)*(eps) eps_b=(3.9)*(eps) \ eps_TMD=((((0.5)*((1)-(typ)))*(5.16))*(eps))+((((0.5)*((1)+(typ)))*(3.3))*(eps)) \ Tnom=27 kb=1.38062e-23 CTOP=(eps_t)/(TTOP) CBOX=(eps_b)/(TBOX) \ lambda=0.1 gamma_e=2 gamma_h=1 FcE=2e+07 FcH=1e+08 \ Fc=(((0.5)*((1)-(typ)))*(FcH))+(((0.5)*((1)+(typ)))*(FcE)) \ vsat0=22000 E_pho=(0.048)*(q) \ F_per_c=(((0.5)*((1)-(typ)))*(3.02e+08))+(((0.5)*((1)+(typ)))*(9e+07)) \ Falpha=(((0.5)*((1)-(typ)))*(6.8))+(((0.5)*((1)+(typ)))*(1.45)) \ Cth=0 kox=1.4 ksi=140 Rcox=1.2e-08 Weff=(W)+((TBOX)*(2)) CTOPh=0 \ Rth_ox=(1)/((((3.14159)*(kox))/(ln((6)*(((TBOX)/(W))+(1)))))+(((kox)/(TBOX))*(W))) \ Rth_int=(Rcox)/(W) Rth_si=((1)/((2)*(ksi)))*(sqrt((L)/(Weff))) \ Rth=(((Rth_ox)+(Rth_int))+(Rth_si))/(L) V1 (net3 0) vsource dc=x type=dc V0 (net4 0) vsource dc=2 type=dc simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf dc dc param=x start=0 stop=10 write="spectre.dc" oppoint=rawfile \ maxiters=150 maxsteps=10000 annotate=status modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save net3 I0:d saveOptions options save=allpub ahdl_include "/home/nano/DIC_project/S2d_new/veriloga/veriloga.va"
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Forum Post: RE: Can I preserve part pin connectivity when using replace cache or link database part in part manager?
sounds like no problem of connectivity here, but a wrong part to replace in cache.
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Forum Post: RE: how can sure a package have multiple parts in orcad capture ?
if you mean text of display prop, part reference is one of that, you can select it, use Move command. copy&paste the following in command window, then try move one, it will show you how it is done. SetOptionBool Journaling TRUE SetOptionBool DisplayCommands TRUE
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Forum Post: RE: RDB Outputs empty and how to plot efficiently in SKILL/Ocean XL
The function i used to plot with is awvPlotWaveform() . Since it seems like you can access your RDB outputs, this should work for you without needing extra code.
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Forum Post: Accessing temperature in an AMS simulation
In Spectre, you can assign a "temp" to a voltage source, and access the simulator temperature as a voltage, but this doesn't work in AMS. Is there a way to do something similar in AMS, to access the current temperature from the simulation?
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Forum Post: RE: Accessing temperature in an AMS simulation
I found this thread that I could use to get the temperature at the start of a simulation, but short of updating it on a periodic basis, I can't see a way to make it continuous https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38379/verilog-a-model-and-temperature-in-ac-sim Also, how do I configure AMS to update the temperature using the "dynamic parameter" control? I tried to vary "temp", and it creates a variable called temp that has no link to the simulator temperature setting
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Forum Post: RE: Standard cell Import issue (spice to schematic) using Spice In import
Hi KC Would you please try "w wf" for propMap instead of "wf w"? Is "l" the name of the of the CDF parameter for nmos3v? Best regards Quek
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Forum Post: RE: WARNING(ORCAP-40202): Pin '2' of comp 'R478' has PINUSE value other than UNSPEC.
never mind, i can remove it, and add it later in sigexplorer.
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Forum Post: RE: cadence gpdk45 off grid problem
This is in gpdk045 v5.0 : UNIX> ls $KITHOME assura/ diva/ gpdk045/ libManager.log pvs/ soce/ assura_tech.lib* docs/ gpdk045.tf models/ pvtech.lib* cds.lib dumpit.cdf lib.defs pmos1v.cdf qrc/ UNIX> ls $KITHOME/docs RELEASE_NOTES gpdk045_PDK_Model_Report.pdf gpdk045_pdk_referenceManual.pdf VERSION gpdk045_drc.pdf The gpdk045_drc.pdf is the document that describes the design rules - quite clearly. Regards, Andrew.
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Forum Post: RE: The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.
It's unclear where the problem lies because there's some line-wrapping in the input.scs which I suspect isn't there in practice. Can you post the input.scs and the VerilogA as an attachment on the post (Insert->Image/video/file) so that I can try it out properly? I assume it's MMSIM13.1 you're using, but can you please provide the exact spectre subversion ("spectre -W" from UNIX will tell you, or it's at the very top of the spectre log file in ADE). Is there a good reason why you're using a 6 year old simulator version? Regards, Andrew.
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Forum Post: RE: Accessing temperature in an AMS simulation
I don't think I understand what you're saying. If you're saying that you can have a vsource output the current temperature converted into a voltage, then that should work with AMS. Is that using tc1 and tc2? The temperature doesn't normally change during the transient unless you use the dynamic parameter control in spectre - and you can use the same mechanism with AMS. What INCISIVE/XCELIUM version are you using for AMS (this should appear in the AMS simulator log)? In VerilogA and VerilogAMS you can also use $temperature to retrieve the current simulator temperature. Regards, Andrew.
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Forum Post: RE: Maintaining two exclusive lists
Ramakrishnan, How about something like this? procedure(moveBin(scrField dstField) let((scrList dstList usedCount) scrList = hiGetListBoxValue(scrField) usedCount = makeTable('usedCount 0) dstList = dstField->choices foreach(ele scrList dstList = cons(ele dstList) usedCount[ele] = usedCount[ele] + 1; ) dstField->choices = dstList scrList = setof(x scrField->choices if(zerop(usedCount[x]) then t else usedCount[x] = usedCount[x] - 1 nil ) ) scrField->choices = scrList )) Regards, Andrew.
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Forum Post: RE: The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.
Please find the input.scs & verilogA file in the link shared below. input.scs verilogA file Spectre subversion-- sub-version 13.1.0.130.isr4
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Forum Post: RE: cadence gpdk45 off grid problem
Hello Andrew, i tried to follow you direction.i get undefined variable problem as shown in the print screen bellow. is there some link from the Cadence website i can use? Anyway Thank you very much for the guidance.
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Forum Post: RE: The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.
Something is very odd about this netlist. It doesn't look to me as if the parameters statements at the top of the input.scs were generated by ADE because there are lots of additional spaces in strange places, and there are line continuation characters missing: Note that I didn't point the arrow at all the missing line continuation characters (just a few). The spaces aren't a problem, but I've not seen ADE do this before. I fixed the missing line continuation characters (I commented out the gpdk model include since they weren't used, but that wouldn't be an issue), and here's the modified file. This simulates fine (I have no idea whether the results are correct - I didn't check - it just runs to completion): community.cadence.com/.../forum67.scs How did the parameters get generated? You mentioned ADE XL - which IC version are you using (Help->About in any window will tell you the subversion)? Perhaps you can show your variable setup in ADE XL? Regards, Andrew.
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Forum Post: RE: cadence gpdk45 off grid problem
Oh, please don't take what I said quite so literally. This is getting to be hard work... I just happened to have $KITHOME pointing at where my gpdk045 installation is (for convenience). I wasn't expecting you to have it set the same way. I was assuming you'd be able to locate where gpdk045 is installed and look for the similar directory. In the CIW, you could do: ddGetObj("gpdk045")~>readPath This will return something like (the path is probably completely different in your environment): "/export/home/myuser/kits/gpdk045_v_5_0/gpdk045" Then if you look in the parent directory (e.g.) /export/home/ myuser /kits/gpdk045_v_5_0/ you should see a "docs" subdirectory and the PDF within that. Regards, Andrew.
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Forum Post: RE: Accessing temperature in an AMS simulation
Apologies, I think I've wasted your time. I couldn't get the dynamic temperature working in AMS yesterday, but it works today doing what I thought I tried yesterday... I wanted to combine that with something that reported the temperature in the simulation, and updated on the dynamic changes. It seems like the @(initial_step) function is updated on the temp changes, which I didn't expect, so that gives me everything I need.
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Forum Post: RE: Drill Chart versus Drill Figures
OK, what is the "assembly detail tool"? I can change the layer for most of the chart by changing the group (and for some reason the external boarder shape individually), but the figures don't change layers. I made a copy of them, but I still could not change the layer. I was able to do this procedure prior to upgrading to version 17.2, but now I can no longer separating the drill chart from the drill figures. There is no issue having the drill figures come up separate from the chart, but not vise versa.
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Forum Post: RE: Drill Chart versus Drill Figures
I found the solution. By selecting the drill chart (via the Group), I could change the layer by selecting the Group, right clicking, and then under Qucik Utilities it allowed me to change the layer in that menu.
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