Hi Bob,All, I am seeing a classic reverse case of above, in my design. No buffers are being added after ICG cells, and the ICG cell output is going to almost 500 flops directly resulting in huge skew and insertion delays. Can someone let me know what might be happening -- I looked at my trace file, and there are only exclude or leaf pins, I dont see any through pins, at all. Thanks, Rajesh.
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Forum Post: RE: clock gating paths
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Forum Post: RE: clock tree synthesis for clock gating
Hi Kari, In my case too, buffering didnt occur after the ICG cell, the ICG cell directly drives around 500 flops spread across the design, resulting in huge skew and latency. I didset the NoGating to be NO, and I removed it too, but it both cases, it didnt make a difference. Any ideas, what might be wrong here. Thanks, Rajesh.'
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Forum Post: [VIRTUOSO] Verilog netlister operation and pin order
Hi community I'd love to get rid of the following issues to enforce mixed analogue <> digital design simulation flow - is it possible to make the netlister generating a (system) verilog where components are instantiated with explici pin assignment e.g. aa i_aa(p0.ww), .p1(yy),...); and not with positional convention - e.g. aa i_aa(ww, yy); - how pin position are assigned in a symbol view? symbol view presents inputs on the left, output on the right without no appearent rule (alphabetila or whatelse ...) so I cannot understand which module declarion is generated/assumed for its verilog counterpart - can I force pin position order in a symbol view? so I can at least make sure that port order during netlist generation will not change every time an analogue engineer changes or regenerates the symbol? thanks much
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Forum Post: RE: OrCad Capture add property from distributor
There are some details here parallel-systems.co.uk/orcadcip or talk to whoever you bought the software from. They can arrange a demo / let you know pricing.
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Forum Post: RE: [VIRTUOSO] Verilog netlister operation and pin order
on enabling the 'explicit' option (which was promising) I see some instance be instantiated with explict portname .a(ww), some others NOT ... is this black magic?
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Forum Post: Create and or Highlight Net Classes in Schematic
I have three questions that are related: 1. If I create net classes in Allegro using CM, is there a way to highlight these net classes in the schematic? 2. To speed creation of net classes in CM, is there a way to highlight nets in schematic and then assign the highlighted nets to a net class in CM? 3. In lieu of #1 and #2, is there a way to create net classes in schematic that will get carried over to the board file and CM? (In a previous life I used PCAD 2000, which had a very intuitive way of dealing with net classes that addressed all of my questions here. I would be surprised if Allegro didn't have similar functionality.) It is very tedious making notes of auto-assigned net names and then assigning them to net classes. I am currently using Allegro version 16.6 and Design Entry CIS.
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Forum Post: RE: hotfix not updating capture?
OK - thanks! Everything I see matches what you've described, as well, so I'll stop worrying about it :)
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Forum Post: PCB Editor Dynamic Etch Shape Issue
I'm running into an odd problem. I have two pins on an SOIC-8 that are next to each other and tied to the same net. I'm trying to lay a dynamic shape over the two pins to connect them together along with some pins on some other parts close by. For some reason, no etch will form between the two pins when I cover them with the shape. What I can do is create a small shape between the two pins. That works until I try to merge the two shapes together. When I do that the shape between the pins disappears. It doesn't seem to be a constraint manager issue. Any suggestions?
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Forum Post: RE: OrCAD PCB Designer Professional 17.2: Rectangle vs. Rectangle Shape
Excellent response! Thank you for the help. I will definitely be saving it in my notes.
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Forum Post: RE: PCB Editor Dynamic Etch Shape Issue
Solved my own problem. I had "Create pin void" set as inline with a 50 mils placing. Reducing the spacing fixed the issue.
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Forum Post: RE: [VIRTUOSO] Verilog netlister operation and pin order
Hi, I believe that the explicit option does not apply to primitive devices, so the non-primitives will be netlisted explicitly, but the primitives use a default port order (something like outputs, inouts, inputs - I think this is documented... Regards, Lawrence.
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Forum Post: RE: [VIRTUOSO] Verilog netlister operation and pin order
Primitives and UDP in Verilog can't be connected to by name, so Lawrence is correct. Also certain split bus configurations are always netlisted implicitly (by order) although I think we do it more often than we need to. If there are other situations you're seeing, I'd suggest you contact customer support so that we can take a look. Regards, Andrew.
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Forum Post: *WARNING* hiDisplayForm:
Hello, I havn't understood this warning: WARNING* hiDisplayForm: cannot display blocking form Generateur_de_Para_Menu before initialization is complete. It is likely that a command in your .cdsinit file is attempting to display the form. Please either change the form to non-blocking (argument "?dontBlock t" to hiCreateAppForm()) or use hiEnqueueCmd() to put the command that displays the form into the command queue and it will be executed once initialization has completed. Someone can explain me what meaning this warning and how can I resolve it? Thank you for your help.
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Forum Post: ADEXL & Ocean Scripts
Hello everybody, I would like to use some ocean scripts to evaluate my simulation results. As Input signals I want to use other output results of ADE-XL (Output expressions). Is this possible in general or do I have to "rebuilt" all signals from base (a=VT("/output1"), ....) ? I've already made a try, but for me it works only in some cases. I'm trying to access the output results by "calcVal(outputName)". For some cases it looks like it doesn't work and I seem to get "Nil" as result. Furthermore I've found this article: https://community.cadence.com/cadence_technology_forums/f/38/t/23684 which indicates to me that this is not possible due to the fact that the script is evaluated by a separate ICRP process). Can anyone give me a hint? Best regards, Markus
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Forum Post: current in subckt cannot be saved, if the subckt is a PEX netlist in Spectre lang format.
Dear all, I have a test bench for just one inverter, as shown below: I want to run postlayout simulation for this inverter, specifically want to save the current flowing into the drain of T0. The parasitics extracted netlist (in Spectre format) of the inverter contains 3 files, and was generated by Calibre xRC: inv.spectre.pex.netlist inv.spectre.pex.netlist.inv.pxi inv.spectre.pex.netlist.pex First, I created the netlist of the test bench using ADE L, and modified it to include the parasitics extracted netlist of the inverter (I0). The netlist is like follows: Second, I saved an ocean script from ADE L, and it looks like this: Note: NMOS T0 in the original cell becomes becomes XMT0 in the extracted netlist, as can be seen in the file "inv.spectre.pex.netlist": When I run this script, the current at terminal "/I0/XMT0/D" is not saved, even though I have specified that in the script. The log file says Output and IC/nodeset summary: save 3 (voltage) And these are just "/OUT" "/CK" "/I0/N_OUT_MT0_d", as specified in the script. No current is saved. I checked that in the result browser as well. Could anybody tell me how to make it work? I found that I can save current in a subckt if the subckt is in Calibre view. However, for a big layout, it takes too much time to generated a Calibre view. To generated a Spectre format extracted netlist is much faster. This is why I want to use Spectre extracted netlist instead. Thank you very much!
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Forum Post: RE: current in subckt cannot be saved, if the subckt is a PEX netlist in Spectre lang format.
PS: I've verified the terminal name "D" in "/I0/XMT0/D" is the name used by the model file.
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Forum Post: RE: current in subckt cannot be saved, if the subckt is a PEX netlist in Spectre lang format.
And my Virtuoso version is IC6.1.7-64b.500.1
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Forum Post: RE: current in subckt cannot be saved, if the subckt is a PEX netlist in Spectre lang format.
If using a name which starts with a "/", you are specifying a schematic name (well, it doesn't have to be a schematic, but it's a name in Virtuoso's namespace). This needs to be mapped (during netlist assembly) to the name that actually appears in the netlist. Given that the subckt for the inv cell is coming from a netlist, it's a name that isn't in the schematic and so can't be mapped by the netlister - you can only use such names for things that were actually netlisted. I think it would work if you used "I0.XMT0:D" or "I0.XMT0:1" (i.e. the native spectre hierarchical names). If a name doesn't begin with a "/" it is assumed to be in the simulator namespace and so isn't mapped. Regards, Andrew.
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Forum Post: RE: *WARNING* hiDisplayForm:
What it means is that you cannot display blocking forms during the .cdsinit file. This used to not raise a warning, and strange things would happen! You either need to add ?dontBlock t to the call to hiCreateAppForm, which makes the form not block SKILL when it's displayed. Alternatively, use: hiEnqueueCmd("hiDisplayForm(Generator_de_Para_Menu)") when you are trying to display it - that will then display it once all the initialisation is complete. Regards, Andrew.
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Forum Post: RE: Virtuoso: Comment Out
Hi Andrew, Thanks again for this reply. Unfortunately I have to go back to IC6.1.6-64b0500.11 now and hence use solution 11523164. Unfortunately it does not work; I do not see any visual representation, SHIFT+F7 does not work and I do get warnings. What I did: I downloaded .ils file and added the following to the end of my .cdsinit: load("CCSignoreInstance.ils") hiSetBindKey("Schematics" " F7" "CCSignoreInstance->ignoreSelected()") hiSetBindKey("Schematics" "Shift F7" "CCSignoreInstance->unignoreSelected()") 1.) When I mark an element in Schematic Editor L and hit F7, indeed the item gets nlAction=ignore property. However, visually nothing changes. 2.) If I hit SHIFT+F7, nothing happens (i.e., the nlAction=ignore ) does not get removed. If I change the key binding for CCSignoreInstance->unignoreSelected() with hiSetBindKey to F6 it works. So it seems either I am hitting SHIFT+F7 the wrong way or it just does not work? 3.) When I manually enter CCSignoreInstance->updateAllWindows() in the CIW I get: CCSignoreInstance->updateAllWindows() *WARNING* (GE-2067): geGetEditCellView: There is no graphical edit environment assigned to window(1) because the window is not a graphic editor window. Make sure that your current window is a valid graphic editor window. If it is a valid graph editor window, contact customer service to investigate this issue. t Not sure it this has anything to do with it. But in my understanding (and hope), all commented elements should have a big red cross above them. Am I doing anything wrong? Thank you! EDIT: Ok, I also need to add CCSignoreInstance->setOption('autoHilight t) to .cdsinit; this fixes (1). However would be happy for a fix on (2) still ...
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