Hi Ummer, The original problem is that I can't open this xsection window.
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Forum Post: RE: Problem with "cross-section" command
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Forum Post: RE: Format of "VCD Info File"
Well ... I've found a description in Appendix E of Spectre® Circuit Simulator and Accelerated Parallel Simulator User Guide and created vcd_info file according to the this document. Here is the content of the vcd_info : .voh 5.0 .vol 0.0 .scope simple_clock(bhv) .out clock where simple_clock(bhv) - the name of digital block entity(architecture) from which I creaed vcd. clock - the only output from the block. At the Virtupso side the schematic is very simple: only one component - resistor, connected to GND at one side, at other - to the floating net named "clock". When I run Spectre, I get the following: Notice from spectre during topology check. Only one connection to the following 2 nodes: 0 clock Error found by spectre during initial setup. ERROR (USIMPRS-17866): No Data read from the vcd file, please verify that the scopes are correct and there are in and/or out vectors specified. Fatal error found by spectre during initial setup. FATAL (SPECTRE-13004):
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Forum Post: RE: Variable overflow
Hi Kean, the problem is that you are using (32bit) integers which are (naturally) limited in their size. Change your code so as it uses floats and off you go... (defun factorial (n) if( zerop( n ) then 1.0 else n*factorial( n-1) ) ; if ) But - a factorial of 5000 is such an incredible number that even floats won't do anymore - 170 is the last one that works, after that you get 'inf' (factorial 170) 7.257416e+306 1> (factorial 171) inf 1> Just outta curiosity,- why would anybody want to compute the factorial of 5000??? Max
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Forum Post: RE: Format of "VCD Info File"
When trying the setup from previous message, I erroneously worked with wrong file. Here is setup that simulates, but still there is no connection between stimuli signal and node in Virtuoso schematic. The top of .vcd file: $comment TOOL: simvision(64) 12.10-s019 $end $date Jul 01, 2019 15:18:55 $end $timescale 1fs $end $scope module simple_clock $end $var wire 1 ! clock1 $end $upscope $end $enddefinitions $end #0 $dumpvars 0! $end #50000000 1! #100000000 0! #150000000 1! #200000000 .......... The content of vcd_info : .hier 1 .voh 5.0 .vol 0.0 .scope simple_clock .out clock1 Note from simulation log: Only one connection to the following 2 nodes: 0 clock1 As result - the clock1 is kept to 0. Any comments. Thanks
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Forum Post: RE: Format of "VCD Info File"
The issue is that you should have used .in rather than .out. From the same document you referenced (right at the beginning): The signal directions are specified in the signal information file. To input signals, Spectre applies stimuli to the simulation. The values of the output signals are used to perform a vector check against the simulation results, and vector errors are generated if mismatches occur I've not really tried the checking capability with Spectre (I know I've used it with UltraSim in the past), but the key point here is that if you're expecting the signal to be driven, you must specify .in so that it's an input signal. Andrew.
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Forum Post: changing a instance of a block across multiples ade assembly schematics
Hi, I'm running IC6.1.7.500.22. I have an ADE assembler cell with multiple schematics, each of them corresponding to a specific maestro test. I have a specific block that is used in all of the tests and I'd like to know if it is possible to change this specific block by another one, in all of the tests, all at once (like a find and replace for multiple schematics). I'm assuming that the replacing block has the same symbol shape and pins of the original block. thanks in advance. best regards,
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Forum Post: viva graph tip
Hi, I'm running IC6.1.7.500.22. I like to know if it is possible to de-activate the popup window of the VIVA Graph tip (see image) every time I start ADE Assembler/Explorer and run a simulation. Even though I have select the Do not show this again , it keeps coming up in new sessions! thanks in advance. best regards,
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Forum Post: Report with List.
Hai, I have two report in that i want generate a new report for equal refdes values i used some codes they were attached below. procedure( compare() out=outfile("report.rpt") in1=infile("report1.rpt") in2=infile("report2.rpt") while(gets (str, in1) if(str != nil then inList = parseString(str ",") a=car(inList) ) ) while(gets (str1, in2) if(str1 != nil then inList = parseString(str1 ",") b=car(inList) (foreach x a (foreach y b if(x == y then fprintf(out,"\n%L",x) ) ) ) ) ) close(out) close(in1) close(in2) ) For this it comes error; E-*Error* foreach: second argumentt must be a list For example Report1: Report2: abc abc bsd bcd ccc ccc Result: abc ccc Please anybody knows share me the skill code i dont know how to do this.
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Forum Post: RE: Problem with "cross-section" command
%HOME% is your home directory, go to pcbenv folder and delete allegro.geo file.
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Forum Post: RE: Star RC Extraction Simulation
Thank you very much for your cooperation. your comment is very helpful for me.
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Forum Post: RE: Format of "VCD Info File"
Thanks Andrew, The case that interests me isn't mentionned in the fragment you quote. i.e. when digital stimuli in .vcd file are applied to Spectre simulator . Or such case isn't taken into consideration by Cadence. Anyway I've tried with .in . The same result
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Forum Post: cdb to oa conversion
I have design which is in cdb version. When I convert the cdb to oa version, the via(M1_M2) sizes are 0.2 for ME1 under "Enclosures" Left and Right. I want 0.08 for Right and Left in ME1. But when I change it to 0.08 it is not changing instead by default it is going back to 0.2 only. I'm using IC 6.1.7 version.
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Forum Post: RE: Format of "VCD Info File"
Well, actually I don't understand what really happens ... I modify the content of the vcd_info and .vcd (e.g. change the name of signal) and rerun simulation, but simulator always shows the same message as if it dodn't see modifications. So after each modification should I close and reopen ADE ?
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Forum Post: RE: Diffstbprobe
Hi Frank, I think the diffstbprobe is the iprobe connected between two ideal_balun. As I remember, I have come across this from your post in some other place long time back. Could you please tell how exactly the connections are with the ideal_balun that works exactly same as that of diffstbprobe. Kind Regards,
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Forum Post: RE: Pointer issue in Layout design
Hello Andrew I am using Cadence Virtuoso Layout Suit Version IC6.1.5 - 64bit. I usually turn off the Gravity option.
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Forum Post: RE: Format of "VCD Info File"
Hit the stop button in ADE. Normally ADE (L) keeps spectre running and most likely it's not refreshing if the contents change. It does work with .in. If I use this: .hier 1 .vih 5.0 .vil 0.0 .scope simple_clock .in clock1 Then I get a signal called simple_clock.clock1 - i.e. a signal inside the hierarchical instance called simple_clock (which gets created if it doesn't exist in your design).You should also use vih/vil rather than voh/vol. It's not going to drive a top level signal called clock1. If you wanted that, you need to use .hier 0 instead. Or add: .alias simple_clock.clock1 clock1 The checking of output vectors does indeed work with spectre (I just checked) - I get a file called input_tran.vecerr with the details of any mismatch between the signals marked as outputs and the actual signals in the simulation - so it's to check that the response is what you expect. For more details, look at the Rapid Adoption Kit Using VEC and VCD files in AMS and Analog Simulation in ADE Regards, Andrew.
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Forum Post: RE: Diffstbprobe
Why do you need to know the internal details? diffstbprobe is effectively two baluns which convert the differential signal into the common-mode and differential-mode part, have an iprobe in each path, and then convert them back to differential again. The simulator then knows which of the two iprobes to pick based on which mode you've asked to measure stability. Andrew
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Forum Post: RE: Pointer issue in Layout design
Trying to guess precisely what you mean just from a description is going to be hard. I would suggest you contact customer support - then we could look at your setup via a web sharing session. Andrew.
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Forum Post: Error detected opening layout file
Hi, #1 ERROR(SPMHNI-178): Error detected opening layout file. The database is corrupted. It may have been copied from a different architecture using ASCII mode ... copy using binary mode.'. #2 Run stopped because errors were detected Kindly help me out to solve this error. Regards Santosh BR
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Forum Post: RE: Diffstbprobe
As far as I can tell, the diffstbprobe internally looks similar to this:
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