Thanks for your reply! The clock period and pulse width are 8u and 4u, respectively. So I set the "Sampling signal/list/step" to 8u. The result doesn't seem to be correct to me. Is there anything that I am missing? Waveform--v("/out" ?result "tran") Sampling signal/list/step--8e-06 Cross Type--rising mode--auto Threshold--0.0 Delay--4.0e-06 Method--end Unit--abs No. of Samples--256
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Forum Post: RE: Calculate DNL of a DAC in Cadence
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Forum Post: Bit pattern generator for mixed signal simulation
Hello, I am using Cadence Virtuoso IC6.1.5 64 bit. In my design I have analog and digital parallel in-parallel out shift register. I need to fill this register with binary data. I am using Verilog to generate my digital data bits by designing functional block and put it in my simulation test bench, then I use to run simulation and set the simulator to 'AMS'. This configuration is not supporting all the simulations as spectra offers. The second thing is that I need to write Verilog code every time I need different type of data. Therefore I would like to ask you please if there is other option provided by cadence to generate pattern of parallel bits (that has configurable times and voltage) which can run under Spectra simulation Thank you Best Regards
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Forum Post: Post-synthesis Simulation Failing when lp_insert_clock_gating true
When I enable clock gating in my synthesis flow (using Genus 18.15), my simulation (using Xcelium) on the post-synthesis netlist fails. The simulation succeeds pre-synthesis and also if I remove clock-gating in the design. I use set_db lp_insert_clock_gating true to enable clock gating during synthesis. I printed out some of the signals from the netlist and can see where it fails (it incorrectly writes a register). However, I am not sure how to solve this issue or what I should be looking for. Any help would be appreciated. Thanks.
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Forum Post: RE: Bit pattern generator for mixed signal simulation
Hi @NirNand I would live to help you with this issue, I can write some SKILL code that can automatically generate this binary data in various formats that will handle both Spice (Spectre,Hspice, AFS) and Digital simulators (Xcelium, vcs). All I aneed is a short spec with an example of a binary file and a snpashot of the testbench. Either post it here or send it over to me at riad at feb22 eda dot com. We can do a quick WebEx if that Suits you. Riad @feb22eda
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Forum Post: Convert "xxxxxb#b" to "xxxxx"
Where "xxxxx" can be any sub string and "#" can be any number. However "#" would rarely be more than two digits. The two "b" characters that are converted to " " are always "b". An example input string would be "abcdb9b" with the required return string being "abcd ". I have a solution that appears work but it's ugly. procedure( charReplace(string) let( ( inDex m1 m2 m3 mb str1 str2 ) inDex = length(lindex(parseString(string "") "b" ?all t)) m1 = pcreCompile( "b[0-9]+b$" ) m2 = pcreCompile( "b$" ) m3 = pcreCompile( "b[0-9]+>$" ) mb = pcreCompile( "b" ) if(pcreExecute(m1 string) then println("match m1") str1 = pcreReplace( m2 string ">" 0) if(pcreExecute(m3 str1) then println("match m3") str2 = pcreReplace( mb str1 " ' and the second to last 'b' with '<'. I worked it out by first creating a new string with the last b (b$) replaced first and then operating on the new string to replace the second to last 'b'. There must be a better way so I'm open to all comments, advice, suggestions, or questions. Thanks in advance and cheers to all.
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Forum Post: Assura probing through Skill
I have a design where I would like to probe some nets. I can load the run and probe nets in the design with the Assura Probing tool. I was wondering if this form calls SKILL commands to perform the probe or is there much more going on than I realize. I have searched the Assura manuals and some Skill manuals but have not found a straightforward way to script the probe. I would like to automate a way to probe a set of signals without the need to enter them one by one in the form. Any help would be greatly appreciated.
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Forum Post: RE: Convert "xxxxxb#b" to "xxxxx"
Hi MorrisDH , What about this ? procedure(charReplace(str) when(pcreMatchp("(.+)b([0-9]+)b$" str) sprintf(nil "%s " pcreSubstitute("\\1") pcreSubstitute("\\2")) ) )
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Forum Post: Drawing level property
I want to extract a design level property using Skill. so that I can assign it to a variable and use it with Set title_Allegro. I have been tring all sorts of axl commands but cannot find the correct one. Any ideas
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Forum Post: RE: Drawing level property
axlDBGetProperties( axlDBGetDesign() "allegro" ) should do it. Other way to access design level properties: axlDBGetDesign()->prop~>?? axlDBGetDesign()->prop->VERSION_ID axlDBGetDesign()->prop->EDIT_TIME etc.
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Forum Post: RE: Drawing level property
Thanks axlDBGetDesign()->prop->VERSION_ID appears to do the job
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Forum Post: RE: place via array acting funny
Submitted help ticket to our VAR and they confirmed it is a bug.
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Forum Post: Trigger a Skill Code by Selecting/Deselecting an Instance in Schematic
Hello, Is there a way to call-back a user defined skill code after I select an instance in schematic. I found a similar question on this forum but they suggest using leRegUserLayerSelectionFilter. This function seems to create a user-defined filter option which is not exactly what I want. Thanks!
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Forum Post: Running Monte Carlo simulations on a statistical corner in ADE XL
Hi, I am attempting to run a mismatch only Monte Carlo simulation on a statistical corner in ADE XL on ICADV12.3, but I get the following error: "ERROR (ADEXL-1751): The 'Monte Carlo Sampling' run mode requires at least one corner other than statistical corners to be enabled for tests." What I am trying to do is take my two worst case corners from a process only Monte Carlo simulation, create two statistical corners, and then run mismatch only Monte Carlo on those corners to observe the overlap. Is it not possible to run monte carlo on a statistical corner? Or do I have to dig through the weeds and create a fixed corner model file from the parameters in my worst case corner? Any information is greatly appreciated. Cheers, Daron
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Forum Post: RE: Convert "xxxxxb#b" to "xxxxx"
That works. I need to read up on pcreSubstitute but that's OK. Thanks,
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Forum Post: Allegro PCB Design - 17.2 2016
Hi, I am trying to update the PCB Layout ( created with he same version 17.2 2016). When I try to change the options in the Display --> Color/Visibility , it Pops out a Window with the following message and when I click OK or close then it shuts down the Allegro PCB Window. Could you please look into this issue and recommend a fix for this issue? Thanks, PM
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Forum Post: Pin connected to shape/line Report
I'm using 17.2 and would like to generate a report that tells me if a component pad is connected to a line or a shape. In the information tool, when selecting a pin, this shows up as "Connected shapes: 1 (TOP)". Is there a way to do this? I don't see this under any of the properties for a Component pin when making a custom report.
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Forum Post: Is there a SKILL code to automatically add labels on wire/path/pathseg on VXL layout IC6.1.7 except for power lines and net###?
Is there a SKILL code to automatically add labels on wire/path/pathseg on VXL layout IC6.1.7 except for power lines and net###?
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Forum Post: RE: Allegro PCB Design - 17.2 2016
Have you run DB Doctor on it? It can be found under the utilities folder. Run it standalone before opening Allegro.
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Forum Post: Ocean Script (AMS simulator): How to save only digital or analog nets
Hi, May I know to modify the following ocean script to save only the digital or analog nets? ocnWaveformTool( 'wavescan ) simulator( 'ams ) solver( 'UltraSim ) ... saveOption( 'netLevelsToSave "all" ) saveOption( 'save "all" ) Regards, Poh Weng
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Forum Post: Layer Information at a point
Is there a skill function to obtain the overlapping layer information at a point say (x,y). Also is it possible to get their database id's. Cadence Version: IC6.1.6
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