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Forum Post: RE: Changing the number of input bits in a DAC and problem in ADE simulation

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Hi Andrew, Thanks for the solution. I am only a beginner to Cadence ecosystem and do not understand many terms used in the code that you shared. It would be of great help if you can tell the procedure of how to create a PCell. E.g. You say that first create a Verilog A view with the content of the code that you shared. I couldn't understand it. Like how does one even do that? Do I need to create a new library, another V-A code? It would be really helpful if there is a step-by-step procedure or a reference where I could look it up. I tried searching these terms in the "The designer's guide to Verilog-AMS" and "Cadence Verilog-A Language Reference" but it was of no use. (No need to explain the code. Just a guide to how to implement it will do.) Thanks. :)

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