Sorry for not making it clear. Here's the steps you need to take: Save the SKILL code above in a file somewhere (note I did just update it because I realised there was a discrepancy in the bus order between the pcell code and the VerilogA in the comments at the top) In the library that you wish to create the component (which I'll call mylib here), either paste the code into a file within that library directory on UNIX and call it "libInit.il" or create a libInit.il with: load("/path/to/theCode.il") Then in the CIW also load the code by calling load("/path/to/theCode.il") (obviously put the actual path in both cases) In the CIW use File->New->CellView and specify the lib/cell as mylib and whatever you want to call the DAC - in my case it was genericDAC . The view should be called "veriloga" and the Type is "VerilogA". Paste the code in the comments at the top of the view into the editor, replacing the template code you get by default. If you've done this in a cell other than "genericDAC" then change the module name at the top of the file to reflect that. Then hit the "Build a database of instances, nets and pins found in the file" icon (the floppy disk/save icon with a green checkmark over it). Then in the CIW enter: abCreateGenericDACViews("DAC" ?cell "genericDAC") (change "genericDAC" to whatever you called the cell) That's it. Now you can place an instance of the symbol of your component, and the bits parameter will alter the width of the input bus pin. Hope that's clear! Regards, Andrew.
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