Forum Post: How do I nc_mirror two enum from VHDL to verilog?

I am trying to nc_mirror some signals from VHDL DUT (non-modifiable) to my SV testbench. There are two VHDL enum state machines which use IDLE. However SV doesnt seem to accept two enums sharing the same element IDLE. What may I do in my testbench to get arround this issue? module tb_probe_abcd; typedef enum integer {IDLE, ST_A, ST_B} t_ab_state; t_ab_state ab_state; typedef enum integer {IDLE, ST_C, ST_D, ST_E } t_cde_state; t_cde_state cde_state; initial begin $nc_mirror("ab_state", "sv_top.dut_wrapper:VHDL_DUT:ab_state"); $nc_mirror("cde_state", "sv_top.dut_wrapper:VHDL_DUT:cde_state"); end endmodule : tb_probe_abcd