Forum Post: RE: Changing the number of input bits in a DAC and problem in ADE...
Glad it worked. Here's how I connected up my test bench - you can specify the bus syntax slightly differently: Regards, Andrew.
View ArticleForum Post: Difference between V(P1,T1)
Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in Verilog A I think V(P1, T1) <+ 0; would mean voltage difference between node P1 and node T1 is 0 and V(P1) <+ V(T1) would mean...
View ArticleForum Post: RE: Unable to import psm path
Sorry for the late responce I tried putting everything flat and it wasn't successful. I tried placing some resistors too and it was showing errors with it and this time the error was E- because...
View ArticleForum Post: ade explorer set instance value
hi, i create one simulation in ade assembler, several test for simulation, for example, i place one analoglib “port” in schematic, but different test need to set different port source type, like dc and...
View ArticleForum Post: RE: Difference between V(P1,T1)
They're not identical - because the first is like having a zero-volt source between the two nets, and the second is like a voltage-controlled voltage source. So that means that in the first case...
View ArticleForum Post: RE: ade explorer set instance value
Well, one way to do this is to have a port (or vsource or isource if that's appropriate - you don't have to use "port" for RF simulations), and set it to sine all the time. Then specify the frequency...
View ArticleForum Post: RE: Assura LVS for Standard Cell Library with only Abstract View
hi Daihyun Would you please try adding ?blackBoxCell avParameter cmd to see if it helps? By the way, this thread has already ended more than 4 years ago. It would be best if you can start a new thread...
View ArticleForum Post: RE: Difference between V(P1,T1)
thank you for your explanation. I am trying to simulate a switch and when I used these statements in an 'if block', I get 'zero diagonal and jacobian' errors. Could you please suggest the best choice...
View ArticleForum Post: how to generate spectre netlist for all the schematics in 1 lib ?
Hi , I would like to generate spectre netlists for all of the schematic cell in my lib. What can I do ? I search in the forum but didn't the answer yet thanks Nhumai
View ArticleForum Post: RE: Difference between V(P1,T1)
If you want an explanation as to why your model misbehaves, it's generally best to actually show your model. My extra-sensory-veriloga-perception isn't working too well at the moment (I blame jet lag),...
View ArticleForum Post: RE: how to generate spectre netlist for all the schematics in 1...
Hi Nhumai, Something like the following (untested) code: simulator('spectre) lib=ddGetObj("libName") foreach(cell lib~>cells when(ddGetObj(lib~>name cell~>name "schematic") design(lib~>name...
View ArticleForum Post: PCB Editor: possible to adjust embedded net names "density"?
Hello! I'd like to increase the "density" of the net names in PCB Editor, as sometimes (specially in close zoomed-in views) large shape areas don't display a label, and one needs to "zoom-out" to catch...
View ArticleForum Post: RE: how to generate spectre netlist for all the schematics in 1...
Hi Andrew, I am new to skill script please help to let me know how to use it ? thanks Nhumai
View ArticleForum Post: RE: how to generate spectre netlist for all the schematics in 1...
Hi Nhumai, Either take the code above (with the correct library name where it has "libName") and paste it in the Command Interpreter Window (CIW), or probably better to put in a file, save the file,...
View ArticleForum Post: How do I nc_mirror two enum from VHDL to verilog?
I am trying to nc_mirror some signals from VHDL DUT (non-modifiable) to my SV testbench. There are two VHDL enum state machines which use IDLE. However SV doesnt seem to accept two enums sharing the...
View ArticleForum Post: RE: Help with exporting .ART with SKILL
I played around and found 1 option that finally worked for me films = axlGetParam("artwork")->groupMembers filmLayers = rexMatchList("^[0-9][0-9][0-9][0-9][0-9]-[0-9]_[A-Z][0-9][0-9]$", films)...
View ArticleForum Post: RE: Unable to import psm path
You can use wildcards in dbdoctor so try browsing for a padstack (filename.pad) then edit it to say \*.pad which will do this as a batch on all padstacks. Repeat for *.dra. That should seed things up.
View ArticleForum Post: RE: NC-Verilog user manual
Hi Stephen, I registered for the support, thank you for this information. Also the trick with the "decompile " in ncsim, worked like a charm. I used the following command: ncdc -output ./mydc.v...
View ArticleForum Post: RE: Replace "`includes" with in-line modules - NC-Verilog
I managed to found the solution. In ncsim environment, after the compilation of the top Verilog netlist, I run the command ncdc -output ./mydc.v my_lib.top:snap and it generated a top Verilog file with...
View ArticleForum Post: RE: NC-Verilog user manual
Great! I'm glad it worked for you, thanks for the update.
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