Hi All, I don't know how to force the netlister to not use positional convention when instantiating modules. I would like the netlister to use the explicit mapping of the signals: example I would like to have: cellname inst_name(.sig1(net1),.sig2(net2)); and not cellname inst_name(net1,net2); I have tried the "Netlist Explicitly" option. I tried the "Generate Pin Mapping" option. But nothing happens. Thanks in advance, Jack.
↧