Forum Post: Plotting Gm vs Vgs in cadence IC6.1.6
Hi, I want to plot gm of a transistor vs vin. Basically gm of a differential pair with input. I read it on this forum where Andrew Beckett suggested to make a file and write save M1:gm and then add it...
View ArticleForum Post: RE: extract netclass of net using extracta
Thanks fxffxf. but the aim of to program that I am writing is to extract data of certain board file without loading it on allegro.
View ArticleForum Post: layout pin creation after binding the devices between schematic...
Hello, I bind between a schematic and its layout using the bndAddInstsBindingByName and lxSetConnRef . So i can select both the nets and the instances between the schematic and layout. How can i create...
View ArticleForum Post: Exposed trace length?
Can someone tell me how exposed length works? I seem to have buried traces that are reporting as exposed. Also, how can I measure exposed length on a given net? TIA. Patrick
View ArticleForum Post: Large selection area of a schematic symbol!...
Hi, I have created a schematic symbol with right area. However, when I select it in my schematic page a large selection area appears that I don't see why?!. I am wondering why selection area exceeds...
View ArticleForum Post: Exclude a coverage on a net
I have asked a question on IMC coverage in 'functional verification' forum. Just posting a link here in case anyone in this forum has any inputs? Regards, Sandeep
View ArticleForum Post: RE: Large selection area of a schematic symbol!...
This is normally related to properties you have added (like Part Number, Value etc. Open the Symbol and look under Options - Part Properties. Any that are displayed can extend the boundary of the...
View ArticleForum Post: RE: Exposed trace length?
It normally shows the length on the outer layers (both TOP and BOTTOM) and is a simple addition of the cline segs. You can use Show Element on Cline Segs (or Clines) and then hover and use the TAB key...
View ArticleForum Post: netlist generation with SystemVerilog netlister plugin
Hi All, I don't know how to force the netlister to not use positional convention when instantiating modules. I would like the netlister to use the explicit mapping of the signals: example I would like...
View ArticleForum Post: Choosing a CPU for best ADE performance
Hi, We're looking to build a workstation computer as part of our (university) research lab for IC design. We're looking to purchase a computer that can run ADE for analog/mixed-signal simulations with...
View ArticleForum Post: @(cross) missing crossing?Why is
Hello: Can someone please tell me what I am doing wrong? code snippet" $strobe("LPIN report: @%rs => ov_check V(lpin, vssa):%r, ov_negate:%r", $abstime, V(lpin, vssa), ov_negate); @(cross((V(lpin,...
View ArticleForum Post: default editor for system verilog file
I need to edit some systemVerilog files in cadence. Currently when I open the file for edit, cadence uses systemVerilog to open it, which is not very convenient to use. So I want to use a different...
View ArticleForum Post: PCB editor assign color is dark
i'm using PCB Editor. i usually like shadow toggle mode for editing. however, it is dark if i assign color on the trace or shape. in other BRD file, it can be shining on the same action. i can't find...
View ArticleForum Post: Clean DFT with tran
Hello, I do get the following distorted DFT plot from my tran simulation: The circuit is the following simple circuit: Note that I can get clean DFT plots with different circuits but I think the caveat...
View ArticleForum Post: RE: OrCAD16.6 DRC check problem: "Net has two or more aliases"
I also have this problem and I do not see any issue with my design either. Browsing the DRC, I see other names have been attached to the concerned power nets. Those "alternative" and confusing aliases...
View ArticleForum Post: Schematic to PCB design
Hi, In my schematic I have connect a Global Power Connector to a "Off-page connector" for our easy understanding of schematic. But both the connectors having different net's when it's imported in...
View ArticleForum Post: RE: Large selection area of a schematic symbol!...
Hi, Thanks for your answer. I checked and updated everything so many times. However, the problem was still exist. Then I decided to remove symbol and add it again. Soon afterwards, it was OK. It seems...
View ArticleForum Post: How to automatically run a user defined procedure after creating...
Hi All I have written a piece of code, to create a table which holds the design version (controlled by a third party tool) of every sub-blocks through design hierarchy. One of the user case is to add...
View ArticleForum Post: RE: PCB editor assign color is dark
Check your Color Settings, Display - Color Visibility - Display folder (or tab in 17.2). Temp Highlight color may be set to black.
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