Hello, I am using Cadence Virtuoso IC6.1.5 64 bit. In my design I have analog and digital parallel in-parallel out shift register. I need to fill this register with binary data. I am using Verilog to generate my digital data bits by designing functional block and put it in my simulation test bench, then I use to run simulation and set the simulator to 'AMS'. This configuration is not supporting all the simulations as spectra offers. The second thing is that I need to write Verilog code every time I need different type of data. Therefore I would like to ask you please if there is other option provided by cadence to generate pattern of parallel bits (that has configurable times and voltage) which can run under Spectra simulation Thank you Best Regards
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