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Forum Post: How to ignore some instances from LVS in layout design

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Hello, I am designing a fully differential amplifier, I am using "Iprobe" to test the CMFB stability by breaking the feedback loop. I am wondering if I want to do the layout and I don't want to remove this probe then LVS will complain, how we can make him to ignore this instance? My Cadence version is IC6.1.5 Thank you

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