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Forum Post: RE: Custom Allegro menus

Yes Dave, can you email to: leswong@juniper.net ? Thanks Les

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Forum Post: RE: Batch waived drc report not finishing

Found it, I need a space after waived_drc !

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Forum Post: RE: Custom Allegro menus

I'm happy to post here: axlUIMenuFind(nil, "about"); Help menu axlUIMenuInsert(nil, "Ed Hickey's Tips and Tricks", "http file:X:/xxxxxx/Tips_Tricks.pdf")

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Forum Post: LVS can't identify layout inductor

Hello Everyone, My inductor in layout can't be identified in assura LVS. As shown below, it shows that inductor is unbound to any layout device. I also tried Calibre LVS, which also has the same...

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Forum Post: RE: Allowing Swapping Pins on the FPGA in Capture 17.2 Hotfix 57

There should be no need to touch the schematic as the backannotation process works on all part types. Yes, it moves the pins on the symbol but no need to move offpage connections. Did I miss something...

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Forum Post: RE: AMS run in tran mode does't not stop at time specified

Thanks Andrew

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Forum Post: RE: IC5141 core dump when launching icfb

Sorry, forgot Ocean version lc-tlva-395{gf925160}586: ocean -W sub-version 5.10.41.500.6.150 lc-tlva-395{gf925160}587: ocean -V @(#)$CDS: awd.exe version 5.1.0 08/25/2011 00:31 (cicln04) $

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Forum Post: RE: Allowing Swapping Pins on the FPGA in Capture 17.2 Hotfix 57

Unfortunately my schematic looks like this, and is one of 10 180-pin headers. The engineer doesn't want the Slot ID (e.g. S15_DP_000) moved. So I can't just backannotate the pin numbers, since that...

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Forum Post: Matlab filtered PRBS inport in Cadence.

Hi Team, I have created a signal in Matlab, which is a Pseudo-Random Binary Sequence (PRBS), Then I FFT the sequence and filter the result in the frequency domain and then reverse FFT to form a...

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Forum Post: RE: How can I close the form using skill code

Hi Vishu Thansks for your reply. yes you are right what i exactly want is once opened the forum then automatically close the forum using skill code instead of , enter ok manually.

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Forum Post: RE: How can I close the form using skill code

Hi Raja, What I have observed is that if you use this function hiFormDone() or hiFormFinish() directly in your script then it won't wait for the users to input the values(if form is created for taking...

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Forum Post: ERROR (SPECTRE-16080): No DC solution found (no convergence).

I got this message in the log file while performing the DC simulation. Please help error found by spectre during DC analysis `dcOp'. ERROR (SPECTRE-16385): There were 8 attempts to find the DC...

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Forum Post: Modgen Editing

Hi, After creating Modgen(placement+routing), when i am trying to delete some vias(which have been incorrectly formed),the routing funtion is invoked again and the via is not getting deleted. Is there...

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Forum Post: RE: Webinar: Writing Good SKILL Code

Thanks Andrew. Great talk.

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Forum Post: RE: Custom Allegro menus

Thanks Dave, we have many custom menus ...

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Forum Post: express_pcell_manager cache saving

Hi all, I have a question: supposing my cell A uses a pCell B from a PDK C. I open layout of A and using express_pcell_manager I save the cache of supermaster B. I then exit the virtuoso session. Later...

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Forum Post: How to ignore some instances from LVS in layout design

Hello, I am designing a fully differential amplifier, I am using "Iprobe" to test the CMFB stability by breaking the feedback loop. I am wondering if I want to do the layout and I don't want to remove...

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Forum Post: Any way to open .BD1 files?

Does anyone have a good way of importing .BD1 files into modern PCB software? A contractor created boards with an ancient copy of DOS based OrCAD and I am having no luck importing them. Tried and...

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Forum Post: RE: Converting Orcad for DOS .BD1 files, tool wanted

I have a similar issue, I have .BD1 files that I have no way to import. VERSION=v203 OrCAD PCB 32bit Board Tried using the 17.2 PCB editor, 15.7 viewer, etc.

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Forum Post: Simulating invertion layer(channel) creation time in MOSFET

Hello, I have an issue that my data falling edge is very close to the clock rising edge, thus logic '1' doesnt get sampled as you can see in the arrows in the last photo so i got to the conclution that...

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