Hi there, I try to run a LVS verification on the top cell of my design. The topcell is made of one core cell and one padring cell. When I run lvs on the core and padring cells individually I get each time a clean 0 error lvs report. Though when I run the lvs one the top cell (core+padring) I get an error from assura saying : *ERROR* There are two or more descriptions of the device with identical type('Generic') and name('presistor') in different libraries, however pin names are not the same, details are given below. 'presistor auLvs analogLib' pin names: [ PLUS MINUS ] dfII terminal names: [ PLUS MINUS ] 'presistor auLvs cmhv7sf' pin names: [ MINUS PLUS ] dfII terminal names: [ MINUS PLUS ] *ERROR* Duplicate device names with different terminal names 'presistor auLvs analogLib [ PLUS MINUS ]' and 'presistor auLvs cmhv7sf [ MINUS PLUS ]' *WARNING* Connection error: The instTerm. sub!, on instance I2 in cell SamPet_Full_v11 schematic SAMPIC_V2_S201611_HIERARCHY does not have a corresponding terminal in the master, subc. 2 error(s) encountered, vldb not generated Error - dfIIToVldb failed to execute Finished /iao_prod/cadence/cdsass415_USR5HF2oa_616/tools.lnx86/assura/bin/nvn *WARNING* An error occurred during Nvn PreExtraction. LVS preprocessing requires a successful run of Nvn. Assura will now terminate. *WARNING* /iao_prod/cadence/cdsass415_USR5HF2oa_616/tools.lnx86/assura/bin/nvn exit with bad status *WARNING* Status 256 *WARNING* Assura execution terminated *WARNING* Bad exit from child process .. 0x100 ***** aveng terminated abnormally ***** *WARNING* aveng exit with bad status *WARNING* Status 256 ***** aveng fork terminated abnormally ***** I run virtuoso 6.1.6 with assura 4.15 HF2 (04.15.102) with tech AMS 018 v4.11. Olivier
↧