Forum Post: arcs converted to line segments during gerber export
So I'm using Allegro 17.2 and have a contoured board outline with several arcs, some that are more of a small radius and others that are a long gentle. I'm trying to create my gerbers but when I do a...
View ArticleForum Post: RE: arcs converted to line segments during gerber export
Well, just got it solved after a suggestion from my mechanical engineer - the arcs had a radius >99mm but my gerber parameters only had 2 integer places which caused the arc radius to become...
View ArticleForum Post: RE: ADE-L Expressions
In this case, you can find the syntax at https://en.wikipedia.org/wiki/%3F:
View ArticleForum Post: RE: Following up the subject of Cadence 16.6 and 17.2
Thank so much everyone. Just wonder if any of you are using EDAC connector from Perception. Try to get it going on Orcad but no luck so far. I could use some help on that. TiBo
View ArticleForum Post: RE: close all views opened by dbOpenCellViewByType()
Hi Ramakrishnan, No, if you call dbSave() first then the save will occur and it would be 'safe' to purge the cellview from virtual memory. Just make sure that you know what you are doing. If there is a...
View ArticleForum Post: RE: IHM_CDT_CALLBACK
Hi Julien, I'm not clear on your terminology but I will take some guesses: IHM => In House Menu? CDT => CDF (typo) and Edit CDT => Edit CDF However, even if my guesses are correct I don't...
View ArticleForum Post: path name
Hi all, I have just start for Place & Route, and I have a problem, After CTS step and CTS_opt step, I see the name of path timing has changed, but number of paths not change. For example, - After...
View ArticleForum Post: name of path timing change
Hi all, I have just start for Place & Route, and I have a problem, After CTS step and CTS_opt step, I see the name of path timing has changed, but number of paths not change. For example, - After...
View ArticleForum Post: On resistance of MOS while sweeping Gate Voltages
hi I want to draw the curve of MOS ON resistance (CS configuration) against all possible values of Gate voltage. I am using Z-parameter analysis to find the R-ON and it gives me single curve against...
View ArticleForum Post: RE: close all views opened by dbOpenCellViewByType()
You might also want to look at using dbGetOpenCellViews() to find out everything that is currently open in memory. Regards, Andrew.
View ArticleForum Post: RE: How to show categories field by default when opening the...
Lawrence, Luis, The .libsel file is related to the library browser not the library manager (the one that is launched when you hit the browse button on forms). So it's not that. You can add:...
View ArticleForum Post: RE: Results Browser: "Append" new "psf's"
Hi Ionut, envSetVal("adexl.plotting" "onlyLoadUserSelectionInResultsBrowser" 'boolean nil) will do this. We've been having a discussion about the best way of making this show up in the user interface...
View ArticleForum Post: I installed a new GF55lpx PDK, and I when I run PVS-QRC, I get...
I'm setting up a new PDK and I have PVS-LVS working. When I generate a QRC(13.2) exrtacted view, I get parasitic- capacitor cells "pcapacitor" and parasitic-resistor cells ="presistor" in the...
View ArticleForum Post: PVS-QRC flow and QRC_Advanced_Modeling licence
Hi, I am having problems setting up Quantus RC extraction using the files generated from PVS-iLVS I am using Virtuoso IC6.17 64bit500.7 Quantus is ext-15.2.3 64bit PVS is 15.16 64bit I obtained the...
View ArticleForum Post: RE: Following up the subject of Cadence 16.6 and 17.2
So what problem are you facing on drawing this connector? Maybe upload the datasheet of the specific one plus what you can't achieve.
View ArticleForum Post: Creating Oblong route keep out
Hi All, I am new to skill code and I am looking for a skill function to creating a Oblong route keep out for a selected object i.e Via or Pins? Thanks in advance! Raj
View ArticleForum Post: RE: IHM_CDT_CALLBACK
Hi Lawrence, thank you for the answer, first of all it's right I did a mistake about the terminology I would say CDF instead CDT but you guessed... "If I followed what you said you were hinting towards...
View ArticleForum Post: Error assura lvs
Hi there, I try to run a LVS verification on the top cell of my design. The topcell is made of one core cell and one padring cell. When I run lvs on the core and padring cells individually I get each...
View ArticleForum Post: RE: On resistance of MOS while sweeping Gate Voltages
documentation could help you to understand: spectre -h save |less # save *:cgg devtype=bsim3v3 HOWTO : create a file, let say : save.scs. In this file, write : save *:ron devtype=bsim3v3 Add this file...
View ArticleForum Post: RE: Following up the subject of Cadence 16.6 and 17.2
Thanks Steve, sorry I did not make it clear, EDAC connector is a third party solfware from Perception that link Orcad capture to Agile. We use EDAC connector to create all part numbers with all new...
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