Forum Post: Building Config tree for System Verilog Testbench when using external HDL

I have a hierarchial external HDL testbench. I am wanting to use the config editor to have a full hierarchy tree of the System Verilog testbench. My issue is that unless I copy the HDL code into individual SV views inside a library in Virtuoso, the instantiated modules within the HDL cannot be found to build the tree view. Is there a way I can have the config tree populate the submodules without having to copy the code into each SV view per module? Thanks!