Hi all, I am new in PLL field. I have some basic questions. How can I make a behavioral model (not phase domain) using verilog AMS to observe everything before going to circuit level. I want to be able to see PLL phase noise using noisy blocks (behavioral) in my system. I know Verilog AMS, but most of the noisy blocks are written with jitter definition and I cannot get a phase noise plot with a jitter noise defined VCO in verilog AMS. I do pss simulation and I guess it is only made for small signal noise. So available VCO verilog AMS codes dont work with pss and pnoise simulation. Lets say If I have a PLL schematic and it works properly. How can I observe the closed loop phase noise ? What kind of simulation I need to run ? Thank you for your time and effort.
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