in the case of using Schematic editor for creating a testbench and ADE Explorer/Assembler for simulating it, I was thinking how can I make my simulations easier when I have to check a variety of input signals in bits/buses and avoid instantiating a lot of vdc generators just to generate one bit-word and similar. I am posting a picture of the idea: In the picture you can see a 4-bit bus line in (the right side), and each bit generated as a single vdc component, and I could have named the dc voltage of each to be a variable (in the picture it isn't) and then those variables would be listed in ADE as design variables. And you would have to label each bit line like in the picture. What do you do if you have a very big testbench and a lot bigger bus lines? On the left side I tried instantiating one vdc component by making an array. It is called V5 , and made a bus called myBus , similarly I made an array of gnd components and noConn components and everything checked without errors. What is left is to create an array of design variables. At this point what would be very neat is to be able to enter vh as a design variable for the DC voltage value, as you can see in the bottom left corner in the Property Editor tab of the V5 generator array. Then when ADE is opened and you want to import design variable from schematic, you would expect to have variables vh , vh and so on... similarly like when you label a bus net. Is this possible? My other solution is to just write a verilogams model I would instantiate with my desired bias signals and then import design parameters from there as variables you pass to a model.
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